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数据搜索系统，热门电子元器件搜索 |
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TNETV1644ZDU6 数据表(PDF) 5 Page - Texas Instruments |
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TNETV1644ZDU6 数据表(HTML) 5 Page - Texas Instruments |
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5 / 306 page  1.3 Functional Block Diagram JTAG Interface System Control PLLs/Clock Generator Input Clock(s) Power/Sleep Controller Pin Multiplexing DSP Subsystem C64x+ t DSP CPU 32 KB L1 Pgm 128 KB L2 RAM 80 KB L1 Data BT.656, Y/C, Raw (Bayer) Video Processing Subsystem (VPSS) CCD Controller Video Interface Front End Resizer Histogram/ 3A Preview 10b DAC On-Screen Display (OSD) Video Encoder (VENC) 10b DAC 10b DAC 10b DAC Back End 8b BT.656, Y/C, 24b RGB NTSC/ PAL, S-Video, RGB, YPbPr Switched Central Resource (SCR) Peripherals EDMA I2C HECC UART Serial Interfaces DDR2 Mem Ctlr (32b) Async EMIF/ NAND/ (8b) Program/Data Storage Watchdog Timer PWM System General- Purpose Timer PCI (33 MHz) VLYNQ EMAC With MDIO Connectivity HPI McASP McBSP OSC Boot ROM 16b GPIO TMS320DM6437 Digital Media Processor www.ti.com SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008 Figure 1-1 shows the functional block diagram of the DM6437 device. Figure 1-1. TMS320DM6437 Functional Block Diagram Submit Documentation Feedback TMS320DM6437 Digital Media Processor 5 |
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