TNETV1644ZDU6 datasheet(87/306 Pages) TI1

87 / 306 page

3.4.1.5 Host Boot Modes

TMS320DM6437

Digital Media Processor

www.ti.com

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

3.4.1.4.2 UART Boot

For UART Boot (BOOTMODE[3:0] = 1000b or 1110b), the bootloader programs the UART0 peripheral as

follows:

• UART0 divisor is set to 15

• Resulting in this UART0 baud rate in kilobit per second (kbps):

–

(CLKIN frequency in MHz) * 1000 / (15 * 16)

The user is responsible for ensuring the resulting baud rate is appropriate for the system. The UART0

divisor (/15) is optimized for CLKIN frequency between 27 to 29 MHz to stay within 5% of the 115200-bps

baud rate.

For more details on the UART peripheral configurations and clock generation, see the TMS320DM643x

DMP Universal Asynchronous Receiver/Transmitter (UART) User's Guide (literature number SPRU997).

3.4.1.4.3 SPI Boot

Both 16-bit address SPI Boot (BOOTMODE = 0110) and 24-bit address SPI boot are performed through

the McBSP0 peripheral. The bootloader programs the McBSP0 peripheral as follows:

• McBSP0 register settings: SRGR.CLKGDV = 2

• Resulting in this SPI serial clock frequency:

–

(SYSCLK3 frequency in MHz) / 3

SYSCLK3 frequency = SYSCLK1 frequency / 6. SYSCLK1 frequency during boot can be found in

Table 3-5, Table 3-6, Table 3-7, and/or Table 3-8 based on the boot mode selection.

For example, if BOOTMODE[3:0] = 0110b, FASTBOOT = 1, the MXI/CLKIN frequency = 27 MHz,

AEM[2:0] = 000b, PLLMS[2:0] = 100b, the combination of Table 3-7 and Table 3-8 indicates that the

device frequency (SYSCLK1) is CLKIN x 22 / 2 = 297 MHz. This means SYSCLK3 frequency is

297 / 6 = 49.5 MHz, resulting in SPI serial clock frequency of 49.5 / 3 = 16.5 MHz.

The DM6437 supports two types of host boots—PCI Boot or HPI Boot.

The PCI Boot (BOOTMODE[3:0] = 0001b or 0010b, PCIEN = 1) is only available in fastboot

(FASTBOOT = 1), as shown in Table 3-6 and Table 3-7.

The HPI Boot is available in fastboot and non-fastboot, as shown in Table 3-5, Table 3-6, and Table 3-7.

Note: The HPI HSTROBE inactive pulse duration timing requirement [tw(HSTBH)] is dependent on the HPI

internal clock source (SYSCLK3) frequency (see Section 6.13.3, HPI Electrical Data/Timing). The external

host must be aware of the SYSCLK3 frequency during boot to ensure the HSTROBE pulse duration

timing requirement is met.

Submit Documentation Feedback

Device Configurations

TNETV1644ZDU6 数据表(PDF) 87 Page - Texas Instruments

TNETV1644ZDU6 数据表(HTML) 87 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载