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3.7 Multiplexed Pin Configurations

TMS320DM6437

Digital Media Processor

www.ti.com

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

DM6437 makes extensive use of pin multiplexing to accommodate a large number of peripheral functions

in the smallest possible package, providing ultimate flexibility for end applications.

The Pin Multiplex Registers PINMUX0 and PINMUX1 in the System Module are responsible for controlling

all pin multiplexing functions on the DM6437. The default setting of some of the PINMUX0 and PINMUX1

bit fields are configured by configuration pins latched at reset (see Section 3.5.1, Device and Peripheral

Configurations at Device Reset). After reset, software may program the PINMUX0 and PINMUX1 registers

to switch pin functionalities.

The following peripherals have multiplexed pins: VPSS (VPFE/VPBE), EMIFA, PCI, HPI, VLYNQ, EMAC,

McASP0, McBSP0, McBSP1, PWM0, PWM1, PWM2, Timer0, Timer1, UART0, UART1, HECC, and GPIO.

The device is divided into the following Pin Multiplexed Blocks (Pin Mux Blocks):

• EMIFA/VPSS Block: VPSS (VPFE/VPBE), EMIFA, part of PCI, GPIO. This block is further subdivided

into these sub-blocks:

–

Sub-Block 0: VPFE (CCDC), part of EMIFA (data, address, control), part of PCI, and GPIO

–

Sub-Block 1: VPBE (VENC), part of EMIFA (data, address, control), and GPIO

–

Sub-Block 2: part of EMIFA (control signals EM_WAIT/(RDY/BSY), EM_OE, and EM_WE)

–

Sub-Block 3: part of EMIFA (address EM_A[12:5]), part of PCI, and GPIO

• Host Block: HPI, VLYNQ, EMAC, part of PCI, and GPIO

• PCI Data Block: part of PCI

• GPIO Block: part of PCI and GPIO

• Serial Port Block: McBSP0, McBSP1, McASP0, and GPIO. This block is further sub-divided into

sub-blocks.

–

Serial Port Sub-Block 0: McBSP0, part of McASP0, and GPIO

–

Serial Port Sub-Block 1: McBSP1, part of McASP0, and GPIO

• UART0 Flow Control Block: UART0 flow control, PWM0, and GPIO

• UART0 Data Block: UART0 data and GPIO

• Timer0 Block: Timer0 and McBSP's CLKS pins

• Timer1 Block: Timer1 and HECC, UART1 data

• PWM1 Block: PWM1 and GPIO

• CLKOUT Block: CLKOUT0, PWM2, and GPIO

As shown in the list above, the PCI, McBSP0, McBSP1, and UART0 peripherals span multiple Pin Mux

Blocks. To use these peripherals, they must be selected in all relevant Pin Mux Blocks. For more details,

see Section 3.7.3, Pin Multiplexing Details, and Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux

Blocks.

Note: There is no actual pin multiplexing in EMIFA/VPSS Sub-Block 2 and the PCI Data Block. However

these are still considered "pin mux blocks" because they contain part of the pins necessary for EMIFA and

PCI, respectively.

A high level view of the Pin Mux Blocks is shown in Figure 3-11. In each Pin Mux Block, the

PINMUX0/PINMUX1 default settings are underlined.

Note: Some default pin functions are determined by configuration pins (PCIEN, AEAW[2:0], AEM[2:0]);

therefore, more than one configuration setting can serve as default based on the configuration pin settings

latched at device reset.

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