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TNETV1644ZDU6 数据表(PDF) 96 Page - Texas Instruments |
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TNETV1644ZDU6 数据表(HTML) 96 Page - Texas Instruments |
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96 / 306 page  3.6.2 Peripheral Selection After Device Reset TMS320DM6437 Digital Media Processor SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008 www.ti.com Table 3-14. MSTPRI0 Register Description (continued) Bit Field Name Description 7:0 RESERVED Reserved. Read-only, writes have no effect. 31 27 26 25 24 23 22 21 20 19 18 17 16 RESERVED PCIP RSV HPIP RSV VLYNQP R-0000 0 R/W-100 R-0 R/W-100 R-0 R/W-100 15 3 2 1 0 RESERVED EMACP R- 0000 0000 0000 0 R/W-100 LEGEND: R = Read; W = Write; -n = value after reset Figure 3-7. MSTPRI1 Register— 0x01C4 0040 Table 3-15. MSTPRI1 Register Description Bit Field Name Description 31:27 RESERVED Reserved. Read-only, writes have no effect. PCI master port priority in System Infrastructure. 000 = Priority 0 (Highest) 100 = Priority 4 26:24 PCIP 001 = Priority 1 101 = Priority 5 010 = Priority 2 110 = Priority 6 011 = Priority 3 111 = Priority 7 (Lowest) 23 RSV Reserved. Read-only, writes have no effect. HPI master port priority in System Infrastructure. 000 = Priority 0 (Highest) 100 = Priority 4 22:20 HPIP 001 = Priority 1 101 = Priority 5 010 = Priority 2 110 = Priority 6 011 = Priority 3 111 = Priority 7 (Lowest) 19 RSV Reserved. Read-only, writes have no effect. VLYNQ master port priority in System Infrastructure. 000 = Priority 0 (Highest) 100 = Priority 4 18:16 VLYNQP 001 = Priority 1 101 = Priority 5 010 = Priority 2 110 = Priority 6 011 = Priority 3 111 = Priority 7 (Lowest) 15:3 RESERVED Reserved. Read-only, writes have no effect. EMAC master port priority in System Infrastructure. 000 = Priority 0 (Highest) 100 = Priority 4 2:0 EMACP 001 = Priority 1 101 = Priority 5 010 = Priority 2 110 = Priority 6 011 = Priority 3 111 = Priority 7 (Lowest) After device reset, most peripheral configurations are done within the peripheral’s registers. This section discusses some additional peripheral controls in the System Module. For information on multiplexed pin controls that determine what peripheral pins are brought out to the pins, see Section 3.7, Multiplexed Pin Configurations. Device Configurations 96 Submit Documentation Feedback |
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