TNETV1644ZDU6 datasheet(35/306 Pages) TI1

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TMS320DM6437

Digital Media Processor

www.ti.com

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

Table 2-11. EMIFA Terminal Functions (EMIFA Pinout Mode 3, AEM[2:0] = 011) (continued)

SIGNAL

TYPE(1)

OTHER(2)(3)

DESCRIPTION

ZWT

ZDU

NAME

NO.

CI0(CCD8)/

EM_A[20]/

IPD

C12

C15

I/O/Z

PINTA/

DVDD33

EM_D[7]/GP[44]

CI1(CCD9)/

EM_A[19]/

IPD

B12

C14

I/O/Z

PREQ/

DVDD33

EM_D[6]/GP[45]

CI2(CCD10)/

EM_A[18]/

IPD

D11

A14

I/O/Z

PRST/

DVDD33

EM_D[5]/GP[46]

CI3(CCD11)/

EM_A[17]/

IPD

A11

B14

I/O/Z

This pin is multiplexed between VPFE (CCDC), EMIFA, PCI, and

AD31/

DVDD33

GPIO.

EM_D[4]/GP[47]

CI4(CCD12)/

For EMIFA (AEM[2:0] = 011], these pins are the 8-bit bi-directional

EM_A[16]/

IPD

data bus (EM_D[7:0]).

C11

B13

I/O/Z

PGNT/

DVDD33

EM_D[3]/GP[48]

CI5(CCD13)/

EM_A[15]/

IPD

B11

C13

I/O/Z

AD29/

DVDD33

EM_D[2]/GP[49]

CI6(CCD14)/

EM_A[14]/

IPD

A10

A13

I/O/Z

AD27/

DVDD33

EM_D[1]/GP[50]

CI7(CCD15)/

EM_A[13]/

IPD

B10

A12

I/O/Z

AD25/

DVDD33

EM_D[0]/GP[51]

This pin is multiplexed between EMIFA, PCI, and GPIO.

EM_A[12]/PCBE3/

IPD

D10

B12

I/O/Z

GP[89]

DVDD33

For EMIFA, it is address bit 12 output EM_A[12].

This pin is multiplexed between EMIFA, PCI, and GPIO.

EM_A[11]/AD24/

IPD

C10

C12

I/O/Z

GP[90]

DVDD33

For EMIFA, it is address bit 11 output EM_A[11].

This pin is multiplexed between EMIFA, PCI, and GPIO.

EM_A[10]/AD23/

IPD

B11

I/O/Z

GP[91]

DVDD33

For EMIFA, it is address bit 10 output EM_A[10].

This pin is multiplexed between EMIFA, PCI, and GPIO.

EM_A[9]/PIDSEL/

IPD

C11

I/O/Z

GP[92]

DVDD33

For EMIFA, it is address bit 9 output EM_A[9].

This pin is multiplexed between EMIFA, PCI, and GPIO.

EM_A[8]/AD21/

IPD

A11

I/O/Z

GP[93]

DVDD33

For EMIFA, it is address bit 8 output EM_A[8].

This pin is multiplexed between EMIFA, PCI, and GPIO.

EM_A[7]/AD22/

IPD

C10

I/O/Z

GP[94]

DVDD33

For EMIFA, it is address bit 7 output EM_A[7].

This pin is multiplexed between EMIFA, PCI, and GPIO.

EM_A[6]/AD20/

IPD

B10

I/O/Z

GP[95]

DVDD33

For EMIFA, it is address bit 6 output EM_A[6].

This pin is multiplexed between EMIFA, PCI, and GPIO.

EM_A[5]/AD19/

IPD

A10

I/O/Z

GP[96]

DVDD33

For EMIFA, it is address bit 5 output EM_A[5].

R0/EM_A[4]/

This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.

IPD

GP[10]/

A17

B21

I/O/Z

DVDD33

For EMIFA, it is address bit 4 output EM_A[4].

(AEAW2/PLLMS2)

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