TNETV1644ZDU6 datasheet(51/306 Pages) TI1

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TMS320DM6437

Digital Media Processor

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SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

Table 2-19. VPFE Terminal Functions

SIGNAL

TYPE(1)

OTHER(2)(3)

DESCRIPTION

ZWT

ZDU

NAME

NO.

VIDEO/IMAGE IN (VPFE)

This pin is multiplexed between the VPFE (CCDC) and GPIO.

IPD

In VPFE mode, this pin is the pixel clock input (PCLK) used to load

PCLK/GP[54]

A14

A18

I/O/Z

DVDD33

image data into the CCD Controller (CCDC) on pins CI[7:0] and

YI[7:0].

This pin is multiplexed between the VPFE (CCDC) and GPIO.

IPD

In VPFE mode, this pin is the vertical synchronization signal (VD) that

VD/GP[53]

A13

A17

I/O/Z

DVDD33

can be either an input (slave mode) or an output (master mode),

which signals the start of a new frame to the CCDC.

This pin is multiplexed between the VPFE (CCDC) and GPIO.

IPD

In VPFE mode, this pin is the horizontal synchronization signal (HD)

HD/GP[52]

A15

A19

I/O/Z

DVDD33

that can be either an input (slave mode) or an output (master mode),

which signals the start of a new line to the CCDC.

This pin is multiplexed between the VPFE (CCDC), EMIFA, PCI, and

GPIO.

CI7(CCD15)/

When used by the CCDC as input CI7, it supports several modes:

EM_A[13]/

IPD

In 16-bit CCD Raw mode, it is input CCD15.

B10

A12

I/O/Z

AD25/

DVDD33

In 16-bit YCbCr mode, it is time multiplexed between CB7 and CR7

EM_D[0]/GP[51]

inputs.(4)

In 8-bit YCbCr mode, it is time multiplexed between Y7, CB7, and

CR7 of the upper 8-bit channel.(4)

This pin is multiplexed between the VPFE (CCDC), EMIFA, PCI, and

GPIO.

CI6(CCD14)/

When used by the CCDC as input CI6, it supports several modes:

EM_A[14]/

IPD

In 16-bit CCD Raw mode, it is input CCD14.

A10

A13

I/O/Z

AD27/

DVDD33

In 16-bit YCbCr mode, it is time multiplexed between CB6 and CR6

EM_D[1]/GP[50]

inputs.(4)

In 8-bit YCbCr mode, it is time multiplexed between Y6, CB6, and

CR6 of the upper 8-bit channel.(4)

This pin is multiplexed between the VPFE (CCDC), EMIFA, PCI, and

GPIO.

CI5(CCD13)/

When used by the CCDC as input CI5, it supports several modes:

EM_A[15]/

IPD

In 16-bit CCD Raw mode, it is input CCD13.

B11

C13

I/O/Z

AD29/

DVDD33

In 16-bit YCbCr mode, it is time multiplexed between CB5, and CR5

EM_D[2]/GP[49]

inputs.(4)

In 8-bit YCbCr mode, it is time multiplexed between Y5, CB5, and

CR5 of the upper 8-bit channel.(4)

This pin is multiplexed between the VPFE (CCDC), EMIFA, PCI, and

GPIO.

CI4(CCD12)/

When used by the CCDC as input CI4, it supports several modes:

EM_A[16]/

IPD

C11

B13

I/O/Z

In 16-bit CCD Raw mode, it is input CCD12.

PGNT/

DVDD33

In 16-bit YCbCr mode, it is time multiplexed between CB4, and CR4

EM_D[3]/GP[48]

inputs.(4)

In 8-bit YCbCr mode, it is time multiplexed between Y4, CB4, and

CR4 of the upper 8-bit channel.(4)

(1)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

(2)

IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external

pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.

(3)

Specifies the operating I/O supply voltage for each signal

(4)

In addition to these default functions, in YCbCr mode, the VPFE CCD Configuration register CCDCFG.YCINSWP bit field allows the

user to swap the function of the YI[7:0] and CI[7:0] pins.

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