TNETV1644ZDU6 datasheet(79/306 Pages) TI1

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3.3.2

VPSS Clocks

TMS320DM6437

Digital Media Processor

www.ti.com

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

The Video Processing SubSystem (VPSS) clocks are controlled via the VPSS_CLKCTL register. The

VPSS_CLKCTL register format is shown in Figure 3-2 and the bit field descriptions are given in Table 3-4.

RESERVED

R-0000 0000 0000 0000

DAC

VEN

PCLK

RESERVED

MUXSEL

CLKEN

INV

R-0000 0000 000

R/W-0

R/W-00

LEGEND: R = Read; W = Write; -n = value after reset

Figure 3-2. VPSS_CLKCTL Register— 0x01C4 0044

Table 3-4. VPSS_CLKCTL Register Description

BIT

NAME

DESCRIPTION

31:5

RESERVED

Reserved. Read-only, writes have no effect.

Video DAC clock enable.

DACCLKEN

0 = DAC clock disabled [default].

1 = DAC clock enabled.

Video Encoder clock enable.

VENCLKEN

0 = VENC clock disabled [default].

1 = VENC clock enabled.

PCLK polarity

PCLKINV

0 = VPSS receives normal PCLK [default].

1 = VPSS receives inverted PCLK.

VPBE (Video Encoder and DAC) clock selection

SETTING

VENC CLK

DAC CLK

00 [default]

27 MHz(a)

54 MHz(b)

1:0

MUXSEL(1)(2)

VPBECLK Input

PCLK (or Inverted PCLK)

OFF

(a) The 27-MHz clock comes from PLLC1 SYSCLKBP.

(b) The 54-MHz clock comes from PLLC2 PLL2_SYSCLK2.

(1)

MUXSEL = 00 selects PLLC1 SYSCLKBP as the clock source to the VPBE. The PLLC1 SYSCLKBP is a 27-MHz clock if the following

settings are true:

MXI/CLKIN clock source is 27 MHz.

PLLC1 Bypass Divider Register (BPDIV) is left at the default setting of divide-by-1.

(2)

MUXSEL = 01 selects PLLC2 PLL2_SYSCLK2 as the clock source to the VPBE. The PLLC2 PLL2_SYSCLK2 is a 54-MHz clock if the

following settings are true:

MXI/CLKIN clock source is 27 MHz.

PLLC2 is in PLL Mode with multiplier x20 to generate a PLL output clock of 27 MHz x 20 = 540 MHz.

PLLDIV2.RATIO is left at the default setting of divide-by-10 to generate SYSCLK2 = 54 MHz.

For more details on the different methods and software sequence to clock (gate) the VPBE components,

see the TMS320DM643x DMP Video Processing Back End (VPBE) User’s Guide (literature number

SPRU952).

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