TNETV1644ZDU6 datasheet(32/306 Pages) TI1

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TMS320DM6437

Digital Media Processor

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

www.ti.com

Table 2-10. EMIFA Terminal Functions (EMIFA Pinout Mode 1, AEM[2:0] = 001) (continued)

SIGNAL

TYPE(1)

OTHER(2)(3)

DESCRIPTION

ZWT

ZDU

NAME

NO.

This pin is multiplexed between EMIFA, PCI, and GPIO.

EM_A[5]/AD19/

IPD

A10

I/O/Z

GP[96]

DVDD33

For EMIFA, this pin is address bit 5 output EM_A[5].

R0/EM_A[4]/

This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.

IPD

GP[10]/

A17

B21

I/O/Z

DVDD33

For EMIFA, this pin is address bit 4 output EM_A[4].

(AEAW2/PLLMS2)

This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.

B0/LCD_FIELD/

IPD

B18

D21

I/O/Z

EM_A[3]/GP[11]

DVDD33

For EMIFA, this pin is address bit 3 output EM_A[3].

B1/EM_A[2]/

This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.

IPD

(CLE)/GP[8]/

B16

A20

I/O/Z

DVDD33

For EMIFA, this pin is address bit 2 output EM_A[2].

(AEAW0/PLLMS0)

G1/EM_A[1]/

This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.

IPD

(ALE)/GP[9]/

A16

B20

I/O/Z

DVDD33

When used for EMIFA, this pin is address output EM_A[1].

(AEAW1/PLLMS1)

This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.

For EMIFA, this pin is Address output EM_A[0], which is the least

R1/ EM_A[0]/

IPD

B17

C21

I/O/Z

significant bit on a 32-bit word address.

GP[7]/(AEM2)

DVDD33

For an 8-bit asynchronous memory, this pin is the 3rd bit of the

address.

COUT0/EM_D0/

IPD

D16

E21

I/O/Z

GP[14]

DVDD33

COUT1/EM_D1/

IPD

D18

G20

I/O/Z

GP[15]

DVDD33

COUT2/EM_D2/

IPD

D17

E22

I/O/Z

GP[16]

DVDD33

These pins are multiplexed between VPBE (VENC), EMIFA, and

COUT3/EM_D3/

IPD

E16

F20

I/O/Z

GPIO.

GP[17]

DVDD33

COUT4/EM_D4/

IPD

For EMIFA (AEM[2:0] = 001), these pins are the 8-bit bi-directional

E18

G21

I/O/Z

GP[18]

DVDD33

data bus (EM_D[7:0]).

COUT5/EM_D5/

IPD

E17

F22

I/O/Z

GP[19]

DVDD33

COUT6/EM_D6/

IPD

F16

F21

I/O/Z

GP[20]

DVDD33

COUT7/EM_D7/

IPD

F17

H20

I/O/Z

GP[21]

DVDD33

EMIFA FUNCTIONAL PINS: 8-Bit NAND (EMIFA Pinout Mode 1, AEM[2:0] = 001)

This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and

G1/EM_A[1]/

GPIO.

IPD

(ALE)/GP[9]/

A16

B20

I/O/Z

DVDD33

When used for EMIFA (NAND) , this pin is the Address Latch Enable

(AEAW1/PLLMS1)

output (ALE).

This pin is multiplexed between VPBE (VENC), EMIFA (NAND), and

B1/EM_A[2]/

GPIO.

IPD

(CLE)/GP[8]/

B16

A20

I/O/Z

DVDD33

When used for EMIFA (NAND), this pin is the Command Latch Enable

(AEAW0/PLLMS0)

output (CLE).

EM_WAIT/

IPU

When used for EMIFA (NAND), this pin is ready/busy input

E15

D20

I/O/Z

(RDY/BSY)

DVDD33

(RDY/BSY).

IPU

EM_OE

D15

D19

I/O/Z

When used for EMIFA (NAND), this pin is read enable output (RE).

DVDD33

IPU

EM_WE

E14

C19

I/O/Z

When used for EMIFA (NAND), this pin is write enable output (WE).

DVDD33

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