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TNETV1644ZDU6 数据表(PDF) 75 Page - Texas Instruments |
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TNETV1644ZDU6 数据表(HTML) 75 Page - Texas Instruments |
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75 / 306 page  TMS320DM6437 Digital Media Processor www.ti.com SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008 Table 3-2. VDD3P3V_PWDN Register Descriptions(1) BIT NAME DESCRIPTION 31:14 RESERVED Reserved. Read-only, writes have no effect. PCI Data Block I/O Power Down Control. Controls the power of the 3 I/O pins in the PCI Data Block. 13 PCIDAT 0 = I/O pins powered up [default]. 1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z). EMIFA/VPSS Sub-Block 3 I/O Power Down Control. Controls the power of the 8 I/O pins in the EMIFA/VPSS Sub-Block 3. 12 EMBK3 0 = I/O pins powered up [default]. 1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z). UART0 Flow Control Block I/O Power Down Control. Controls the power of the 2 I/O pins in the UART0 Flow Control Block. 11 UR0FC 0 = I/O pins powered up. 1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z) [default]. UART0 Data Block I/O Power Down Control. Controls the power of the 2 I/O pins in the UART0 Data Block. 10 UR0DAT 0 = I/O pins powered up. 1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z) [default]. Timer1 Block I/O Power Down Control. Controls the power of the 2 I/O pins in the Timer1 Block. 9 TIMER1 0 = I/O pins powered up. 1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z) [default]. Timer0 Block I/O Power Down Control. Controls the power of the 2 I/O pins in the Timer0 Block. 8 TIMER0 0 = I/O pins powered up. 1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z) [default]. Serial Port Block I/O Power Down Control. Controls the power of the 12 I/O pins in the Serial Port Block (Serial Port Sub-Block 0 and Serial Port Sub-Block 1). 7 SP 0 = I/O pins powered up. 1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z) [default]. PWM1 Block I/O Power Down Control. Contros thel power of the 1 I/O pin in the PWM1 Block. 6 PWM1 0 = I/O pins powered up. 1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z) [default]. GPIO Block I/O Power Down Control. Controls the power of the 4 I/O pins in the GPIO Block. 5 GPIO 0 = I/O pins powered up [default]. 1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z). Host Block I/O Power Down Control. Controls the power of the 27 I/O pins in the Host Block. 4 HOST 0 = I/O pins powered up [default]. 1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z). EMIFA/VPSS Sub-Block 2 I/O Power Down Control. Controls the power of the 3 I/O pins in the EMIFA/VPSS Sub-Block 2. 3 EMBK2 0 = I/O pins powered up [default]. 1 = I/O pins powered down and not operational. Outputs are 3-stated (Hi-Z). (1) For more details on I/O pins belonging to each pin mux block, see Section 3.7, Multiplexed Pin Configurations. Submit Documentation Feedback Device Configurations 75 |
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