TNETV1644ZDU6 datasheet(102/306 Pages) TI1

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3.7.2

Pin Muxing Selection After Reset

3.7.2.1 PINMUX0 Register Description

TMS320DM6437

Digital Media Processor

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

www.ti.com

The PINMUX0 and PINMUX1 registers in the System Module allow software to select the pin functions in

the Pin Mux Blocks. The pin control of some of the Pin Mux Blocks requires a combination of

PINMUX0/PINMUX1 bit fields. For more details on the combination of the PINMUX bit fields that control

each muxed pin, see Section 3.7.3.1, Multiplexed Pins on DM6437.

This section only provides an overview of the PINMUX0 and PINMUX1 registers. For more detailed

discussion on how to program each Pin Mux Block, see Section 3.7.3, Pin Multiplexing Details.

The Pin Multiplexing 0 Register (PINMUX0) controls the pin function in the EMIFA/VPSS Block. The

PINMUX0 register format is shown in Figure 3-12 and the bit field descriptions are given in Table 3-19.

Some muxed pins are controlled by more than one PINMUX bit field. For the combination of the PINMUX

bit fields that control each muxed pin, see Section 3.7.3.1, Multiplexed Pins on DM6437. For more

information on EMIFA/VPSS Block pin muxing, see Section 3.7.3.13, EMIFA/VPSS Block Muxing. For the

pin-by-pin muxing control of the EMIFA/VPSS Block, see Section 3.7.3.13.7, EMIFA/VPSS Block

Pin-By-Pin Multiplexing Summary.

Note: In addition to PINMUX0 bit fields, the EMIFA/VPSS Block also requires the PCIEN bit in the Pin

Multiplexing 1 Register (PINMUX1, Section 3.7.2.2) to determine the PCI settings.

CFLDSE

CWEN

CCDCSE

RSV

CI10SEL

RSV

CI32SEL

RSV

CI54SEL

CI76SEL

HVDSEL

RSV

AEAW

SEL

R/W-0

R/W-LLL

VPBE

RGBSEL

CS3SEL

CS4SEL

CS5SEL

VENCSEL

RSV

AEM

CKEN

R/W-0

R/W-000

R/W-00

R/W-0

R/W-LLL

LEGEND: R/W = Read/Write; R = Read only; L = pin state latched at reset rising edge; -n = value after reset

(1) For proper DM6437 device operation, always write a value of "0" to all RESERVED/RSV bits.

Figure 3-12. PINMUX0 Register— 0x01C4 0000 (1)

Table 3-19. PINMUX0 Register Descriptions

Bit

Field Name

Description

Pins Controlled

Reserved. For proper device operation, the user should only write "0" to this bit

RSV

(default).

CI[1:0] Function Select.

Sub-Block 0

0 = No CCDC CI[1:0].

CI1(CCD9)/EM_A[19]/PREQ/EM_D[6]/GP[45]

Pins function as PCI or GPIO or EMIFA based on AEM, AEAW, and PCIEN

settings (default).

CI0(CCD8)/EM_A[20]/PINTA/EM_D[7]/GP[44]

CI10SEL

1 = Selects CCDC [1:0] (as CCD8 and CCD9, respectively) to get at least a 10-bit

The combination of PINMUX0/1 fields AEM,

CCDC.

AEAW, PCIEN, and CI10SEL bits control the

To use the 10-bit CCDC, the user must also configure PINMUX0.CCDCSEL = 1.

pin muxing of these 2 pins. (1)

Not applicable (N/A) for AEM = 3 (011b), 4 (100b), or PCIEN = 1.

Reserved. For proper device operation, the user should only write "0" to this bit

RSV

(default).

(1)

For the full set of valid configurations of these pins, see Section 3.7.3.13.7, EMIFA/VPSS Block Pin-By-Pin Multiplexing Summary.

102

Device Configurations

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