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TNETV1644ZDU6 数据表(PDF) 105 Page - Texas Instruments

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部件名 TNETV1644ZDU6
功能描述  Digital Media Processor
PDF  306 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TNETV1644ZDU6 数据表(HTML) 105 Page - Texas Instruments

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TMS320DM6437
Digital Media Processor
www.ti.com
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
Table 3-19. PINMUX0 Register Descriptions (continued)
Bit
Field Name
Description
Pins Controlled
Chip Select 3 Select.
Sub-Block 1
00 = GPIO pin (GP13) (default)
LCD_OE/EM_CS3/GP[13]
11:10
CS3SEL
01 = EMIFA Chip Select 3 (EM_CS3)
The PINMUX0 field CS3SEL alone controls the
10 = VENC LCD Output Enable (LCD_OE)
muxing of this pin.
11 = Reserved
Chip Select 4 Select.
Sub-Block 1
00 = GPIO pin (GP32) (default)
VSYNC/EM_CS4/GP[32]
9:8
CS4SEL
01 = EMIFA Chip Select 4 (EM_CS4)
The PINMUX0 field CS4SEL alone controls the
10 = VENC Vertical Sync (VSYNC)
muxing of this pin.
11 = Reserved
Chip Select 5 Select.
Sub-Block 1
00 = GPIO pin (GP33) (default)
HSYNC/EM_CS5/GP[33]
7:6
CS5SEL
01 = EMIFA Chip Select 5 (EM_CS5)
The PINMUX0 field CS5SEL alone controls the
10 = VENC Horizontal Sync (HSYNC)
muxing of this pin.
11 = Reserved
Sub-Block 1
VCLK/GP[31]
YOUT7/GP[29]
YOUT6/GP[28]
YOUT5/GP[27]
VENC Mode Select.
YOUT4/GP[26]
YOUT3/GP[25]
00 = No VENC supported.
YOUT2/GP[24]
9 pins function as GPIO (GP[31], GP[29:22]). The remaining 8 pins function as
YOUT1/GP[23]
GPIO/EMIFA based on AEM setting.
YOUT0/GP[22]
01 = 8-bit VENC supported.
The PINMUX0 field VENCSEL alone controls
5:4
VENCSEL
VENC VCLK, YOUT[7:0] functions are pinned out. The remaining 8 pins function
the muxing of these 9 pins.
as GPIO/EMIFA based on AEM setting.
COUT7/EM_D[7]/GP[21]
10 = 16-bit VENC supported.
COUT6/EM_D[6]/GP[20]
These pins function as VENC VCLK, YOUT[7:0], and COUT[7:0].
COUT5/EM_D[5]/GP[19]
Applicable only if AEM = 0 (000b), 3 (011b), 4 (100b).
COUT4/EM_D[4]/GP[18]
COUT3/EM_D[3]/GP[17]
11 = Reserved
COUT2/EM_D[2]/GP[16]
COUT1/EM_D[1]/GP[15]
COUT0/EM_D[0]/GP[14
The combination of PINMUX fields VENCSEL
and AEM control the muxing of these 8 pins.(1)
Reserved. For proper device operation, the user should only write "0" to this bit
3
RSV
(default).
Submit Documentation Feedback
Device Configurations
105



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