TNETV1644ZDU6 datasheet(121/306 Pages) TI1

121 / 306 page

TMS320DM6437

Digital Media Processor

www.ti.com

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

As discussed in Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks, the UART0 pins span

across two Pin Mux Blocks: UART0 Data Block, and UART0 Flow Control Block. For proper UART0

operation, the two pins in the UART0 Data Block must be configured for UART0 data functions. The two

pins in the UART0 Flow Control Block are optional.

Table 3-30 provides a different view of the UART0 Flow Control Block pin muxing, showing the UART0

Flow Control Block function based on PINMUX1.UR0FCBK setting. The selection options are also shown

pictorially in Figure 3-11.

Table 3-30. UART0 Flow Control Block Function Selection

PINMUX1.UR0FCBK

BLOCK FUNCTION

RESULTING PIN FUNCTIONS

GPIO (2) (default)

GPIO: GP[88:87]

UART0 Flow Control

UART0: UCTS0, URTS0

PWM0: PWM0

PWM0 + GPIO (1)

GPIO: GP[87]

Reserved

In addition, the VDD3P3V_PWDN.UR0FC field determines the power state of the UART0 Flow Control

Block pins. The UART0 Flow Control Block pins default to powered down and not operational. To use

these pins, user must first program VDD3P3V_PWDN.UR0FC = 0 to power up the pins. For more details

on the VDD3P3V_PWDN.UR0FC field, see Section 3.2, Power Considerations.

The UART0 Flow Control Block features internal pullup resistors, which matches the UART inactive

polarity.

Submit Documentation Feedback

Device Configurations

121

TNETV1644ZDU6 数据表(PDF) 121 Page - Texas Instruments