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SPC560P34L1 数据表(PDF) 77 Page - STMicroelectronics |
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SPC560P34L1 数据表(HTML) 77 Page - STMicroelectronics |
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77 / 103 page ![]() SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3 Electrical characteristics Doc ID 16100 Rev 7 77/103 Figure 19. Pad output delay 3.17 AC timing characteristics 3.17.1 RESET pin characteristics The SPC560P34/SPC560P40 implements a dedicated bidirectional RESET pin. ttr CC D Output transition time output pin(2) FAST configuration CL = 25 pF VDD = 5.0 V ± 10%, PAD3V5V = 0 SIUL.PCRx.SRC = 1 —— 4 ns CL = 50 pF — — 6 CL = 100 pF — — 12 CL = 25 pF VDD = 3.3 V ± 10%, PAD3V5V = 1 SIUL.PCRx.SRC = 1 —— 4 CL = 50 pF — — 7 CL = 100 pF — — 12 tSYM (3) CC T Symmetric transition time, same drive strength between N and P transistor VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 4 ns VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 5 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 °C to TA MAX, unless otherwise specified. 2. CL includes device and package capacitances (CPKG < 5 pF). 3. Transition timing of both positive and negative slopes will differ maximum 50%. Table 36. Output pin transition times (continued) Symbol C Parameter Conditions(1) Value Unit Min Typ Max VDD_HV_IOx/2 VOH VOL Rising Edge Output Delay Falling Edge Output Delay Pad Data Input Pad Output |
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