SPC560P34L1 datasheet(11/103 Pages) STMICROELECTRONICS

11 / 103 page

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

Introduction

Doc ID 16100 Rev 7

11/103

Table 4.

SPC560P34/SPC560P40 series block summary

Block

Function

Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to-digital converter

Boot assist module (BAM)

Block of read-only memory containing VLE code which is executed according to

the boot mode of the device

Clock generation module

(MC_CGM)

Provides logic and control required for the generation of system and peripheral

clocks

Controller area network

(FlexCAN)

Supports the standard CAN communications protocol

Cross triggering unit (CTU)

Enables synchronization of ADC conversions with a timer event from the

eMIOS or from the PIT

Crossbar switch (XBAR)

Supports simultaneous connections between two master ports and three slave

ports; supports a 32-bit address bus width and a 32-bit data bus width

Cyclic redundancy check (CRC)

CRC checksum generator

Deserial serial peripheral

interface (DSPI)

Provides a synchronous serial interface for communication with external

devices

Enhanced direct memory access

(eDMA)

Performs complex data transfers with minimal intervention from a host

processor via “n” programmable channels

Enhanced timer (eTimer)

Provides enhanced programmable up/down modulo counting

Error correction status module

(ECSM)

Provides a myriad of miscellaneous control functions for the device including

program-visible information about configuration and revision levels, a reset

status register, wakeup control for exiting sleep modes, and optional features

such as information on memory errors reported by error-correcting codes

External oscillator (XOSC)

Provides an output clock used as input reference for FMPLL_0 or as reference

clock for specific modules depending on system needs

Fault collection unit (FCU)

Provides functional safety to the device

Flash memory

Provides non-volatile storage for program code, constants and variables

Frequency-modulated phase-

locked loop (FMPLL)

Generates high-speed system clocks and supports programmable frequency

modulation

Interrupt controller (INTC)

Provides priority-based preemptive scheduling of interrupt requests

JTAG controller

Provides the means to test chip functionality and connectivity while remaining

transparent to system logic when not in test mode

LINFlex controller

Manages a high number of LIN (Local Interconnect Network protocol)

messages efficiently with a minimum of CPU load

Mode entry module (MC_ME)

Provides a mechanism for controlling the device operational mode and mode

transition sequences in all functional states; also manages the power control

unit, reset generation module and clock generation module, and holds the

configuration, control and status registers accessible for applications

Periodic interrupt timer (PIT)

Produces periodic interrupts and triggers

Peripheral bridge (PBRIDGE)

Is the interface between the system bus and on-chip peripherals

Power control unit (MC_PCU)

Reduces the overall power consumption by disconnecting parts of the device

from the power supply via a power switching device; device components are

grouped into sections called “power domains” which are controlled by the PCU

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