SPC560P34L1 datasheet(15/103 Pages) STMICROELECTRONICS

15 / 103 page

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

Introduction

Doc ID 16100 Rev 7

15/103

The flash memory module provides the following features:

●

As much as 320 KB flash memory

–

6 blocks (32 KB + 2×16 KB + 32 KB + 32 KB + 128 KB) code flash memory

–

4 blocks (16 KB + 16 KB + 16 KB + 16 KB) data flash memory

–

Full Read-While-Write (RWW) capability between code flash memory and data

flash memory

●

Four 128-bit wide prefetch buffers to provide single cycle in-line accesses (prefetch

buffers can be configured to prefetch code or data or both)

●

Typical flash memory access time: no wait-state for buffer hits, 2 wait-states for page

buffer miss at 64 MHz

●

Hardware managed flash memory writes handled by 32-bit RISC Krypton engine

●

Hardware and software configurable read and write access protections on a per-master

basis

●

Configurable access timing allowing use in a wide range of system frequencies

●

Multiple-mapping support and mapping-based block access timing (up to 31 additional

cycles) allowing use for emulation of other memory types

●

Software programmable block program/erase restriction control

●

Erase of selected block(s)

●

Read page sizes

–

Code flash memory: 128 bits (4 words)

–

Data flash memory: 32 bits (1 word)

●

ECC with single-bit correction, double-bit detection for data integrity

–

Code flash memory: 64-bit ECC

–

Data flash memory: 32-bit ECC

●

Embedded hardware program and erase algorithm

●

Erase suspend and program abort

●

Censorship protection scheme to prevent flash memory content visibility

●

Hardware support for EEPROM emulation

1.5.5

Static random access memory (SRAM)

The SPC560P34/SPC560P40 SRAM module provides up to 20 KB of general-purpose

memory.

The SRAM module provides the following features:

●

Supports read/write accesses mapped to the SRAM from any master

●

Up to 20 KB general purpose SRAM

●

Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of

memory

●

Typical SRAM access time: no wait-state for reads and 32-bit writes; 1 wait-state for 8-

and 16-bit writes if back-to-back with a read to same memory block

SPC560P34L1 数据表(PDF) 15 Page - STMicroelectronics

SPC560P34L1 数据表(HTML) 15 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载