SPC560P34L1 datasheet(25/103 Pages) STMICROELECTRONICS

25 / 103 page

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

Introduction

Doc ID 16100 Rev 7

25/103

1.5.25

eTimer

The SPC560P34/SPC560P40 includes one eTimer module which provides six 16-bit

general purpose up/down timer/counter units with the following features:

●

Clock frequency same as that used for the e200z0h core

●

Individual channel capability

–

Input capture trigger

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Output compare

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Double buffer (to capture rising edge and falling edge)

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Separate prescaler for each counter

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Selectable clock source

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0–100% pulse measurement

–

Rotation direction flag (quad decoder mode)

●

Maximum count rate

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External event counting: max. count rate = peripheral clock/2

–

Internal clock counting: max. count rate = peripheral clock

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Counters are:

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Cascadable

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Preloadable

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Programmable count modulo

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Quadrature decode capabilities

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Counters can share available input pins

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Count once or repeatedly

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Pins available as GPIO when timer functionality not in use

1.5.26

Analog-to-digital converter (ADC) module

The ADC module provides the following features:

Analog part:

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1 on-chip analog-to-digital converter

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10-bit AD resolution

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1 sample and hold unit

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Conversion time, including sampling time, less than 1 µs (at full precision)

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Typical sampling time is 150 ns minimum (at full precision)

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DNL/INL ±1 LSB

–TUE < 1.5 LSB

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Single-ended input signal up to 3.3 V/5.0 V

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3.3 V/5.0 V input reference voltage

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ADC and its reference can be supplied with a voltage independent from VDDIO

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ADC supply can be equal or higher than VDDIO

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ADC supply and ADC reference are not independent from each other (both

internally bonded to same pad)

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Sample times of 2 (default), 8, 64 or 128 ADC clock cycles

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