SPC560P34L1 datasheet(27/103 Pages) STMICROELECTRONICS

27 / 103 page

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

Introduction

Doc ID 16100 Rev 7

27/103

The development support provided includes access to the MCU’s internal memory map and

access to the processor’s internal registers.

The NDI provides the following features:

●

Configured via the IEEE 1149.1

●

All Nexus port pins operate at VDDIO (no dedicated power supply)

●

Nexus Class 1 supports Static debug

1.5.29

Cyclic redundancy check (CRC)

The CRC computing unit is dedicated to the computation of CRC off-loading the CPU. The

CRC module features:

●

Support for CRC-16-CCITT (x25 protocol):

–

x16 + x12 + x5 + 1

●

Support for CRC-32 (Ethernet protocol):

–

x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1

●

Zero wait states for each write/read operations to the CRC_CFG and CRC_INP

registers at the maximum frequency

1.5.30

IEEE 1149.1 JTAG controller

The JTAG controller (JTAGC) block provides the means to test chip functionality and

connectivity while remaining transparent to system logic when not in test mode. All data

input to and output from the JTAGC block is communicated in serial format. The JTAGC

block is compliant with the IEEE standard.

The JTAG controller provides the following features:

●

IEEE test access port (TAP) interface 4 pins (TDI, TMS, TCK, TDO)

●

Selectable modes of operation include JTAGC/debug or normal system operation.

●

5-bit instruction register that supports the following IEEE 1149.1-2001 defined

instructions:

–

BYPASS

–

IDCODE

–EXTEST

–

SAMPLE

–

SAMPLE/PRELOAD

●

5-bit instruction register that supports the additional following public instructions:

–

ACCESS_AUX_TAP_NPC

–

ACCESS_AUX_TAP_ONCE

●

3 test data registers:

–

Bypass register

–

Boundary scan register (size parameterized to support a variety of boundary scan

chain lengths)

–

Device identification register

●

TAP controller state machine that controls the operation of the data registers,

instruction register and associated circuitry

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