SPC560P34L1 datasheet(79/103 Pages) STMICROELECTRONICS

79 / 103 page

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

Electrical characteristics

Doc ID 16100 Rev 7

79/103

Table 37.

RESET electrical characteristics

Symbol

Parameter

Conditions(1)

Value(2)

Unit

Min

Typ

Max

VIH

Input high level CMOS

(Schmitt Trigger)

—0.65VDD

—VDD +0.4

VIL

Input low level CMOS

(Schmitt Trigger)

—

−0.4

—

0.35VDD

VHYS

Input hysteresis CMOS

(Schmitt Trigger)

—0.1VDD

——

VOL

POutput low level

Push Pull, IOL = 2 mA,

VDD = 5.0 V ± 10%, PAD3V5V = 0

(recommended)

—

0.1VDD

Push Pull, IOL = 1 mA,

VDD = 5.0 V ± 10%, PAD3V5V = 1

(3)

—

0.1VDD

Push Pull, IOL = 1 mA,

VDD = 3.3 V ± 10%, PAD3V5V = 1

(recommended)

——

0.5

ttr

Output transition time

output pin(4) MEDIUM

configuration

CL = 25 pF,

VDD = 5.0 V ± 10%, PAD3V5V = 0

——

CL = 50 pF,

VDD = 5.0 V ± 10%, PAD3V5V = 0

——

CL = 100 pF,

VDD = 5.0 V ± 10%, PAD3V5V = 0

——

CL = 25 pF,

VDD = 3.3 V ± 10%, PAD3V5V = 1

——

CL = 50 pF,

VDD = 3.3 V ± 10%, PAD3V5V = 1

——

CL = 100 pF,

VDD = 3.3 V ± 10%, PAD3V5V = 1

——

WFRST

RESET input filtered

pulse

——

—

WNFRST

RESET input not

filtered pulse

—

500

—

tPOR

Maximum delay before

internal reset is

released after all

VDD_HV reach nominal

supply

Monotonic VDD_HV supply ramp

—

|IWPU|

Weak pull-up current

absolute value

VDD = 3.3 V ± 10%, PAD3V5V = 1

—

150

µA

VDD = 5.0 V ± 10%, PAD3V5V = 0

—

150

VDD = 5.0 V ± 10%, PAD3V5V = 1

(5)

—

250

VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = −40 to 125 °C, unless otherwise specified

All values need to be confirmed during device validation.

This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of device

reference manual).

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