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ST7MC1K2-Auto 数据表(PDF) 115 Page - STMicroelectronics |
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ST7MC1K2-Auto 数据表(HTML) 115 Page - STMicroelectronics |
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115 / 371 page  Obsolete Product(s) - Obsolete Product(s) ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto On-chip peripherals 115/371 Figure 50. One pulse mode sequence When a valid event occurs on the ICAP1 pin, the counter value is loaded in the ICR1 register. The counter is then initialized to FFFCh, the OLVL2 bit is output on the OCMP1 pin and the ICF1 bit is set. Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set. Clearing the input capture interrupt request (that is, clearing the ICFi bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. Accessing (reading or writing) the ICiLR register. The OC1R register value required for a specific timing application can be calculated using the following formula: Equation 3 Where: If the timer clock is an external clock the formula is: Equation 4 Where: When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin, (see Figure 51). t = pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see Table 51) t = pulse period (in seconds) fEXT = external timer clock frequency (in hertz) occurs on counter = OC1R OCMP1 = OLVL1 When When event ICAP1 One pulse mode cycle OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set ICR1 = counter OCiR value = t * fCPU PRESC - 5 OCiR= t * fEXT -5 Obsolete Product(s) - Obsolete Product(s) |
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