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ST7MC1K2-Auto 数据表(PDF) 116 Page - STMicroelectronics |
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ST7MC1K2-Auto 数据表(HTML) 116 Page - STMicroelectronics |
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116 / 371 page  Obsolete Product(s) - Obsolete Product(s) On-chip peripherals ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto 116/371 Note: 1 The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate an output compare interrupt. 2 When the pulse width modulation (PWM) and one pulse mode (OPM) bits are both set, the PWM mode is the only active one. 3 If OLVL1 = OLVL2 a continuous signal is seen on the OCMP1 pin. 4 The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set. 5 When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and OCF2 can be used to indicate a period of time has been elapsed but cannot generate an output waveform because the level OLVL2 is dedicated to the one pulse mode. Figure 51. One pulse mode timing example 1. IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1 Figure 52. Pulse width modulation mode timing example 1. OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1 Pulse width modulation mode Pulse width modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. Pulse width modulation mode uses the complete output compare 1 function plus the OC2R register, and so this functionality can not be used when PWM mode is activated. In PWM mode, double buffering is implemented on the output compare registers. Any new values written in the OC1R and OC2R registers are loaded in their respective shadow registers (double buffer) only at the end of the PWM period (OC2) to avoid spikes on the PWM output pin (OCMP1). The shadow registers contain the reference values for comparison in PWM ‘double buffering’ mode. Counter FFFC FFFD FFFE 2ED0 2ED1 2ED2 2ED3 FFFC FFFD OLVL2 OLVL2 OLVL1 ICAP1 OCMP1 Compare1 01F8 01F8 2ED3 IC1R Counter 34E2 34E2 FFFC OLVL2 OLVL2 OLVL1 OCMP1 Compare2 Compare1 Compare2 FFFC FFFD FFFE 2ED0 2ED1 2ED2 Obsolete Product(s) - Obsolete Product(s) |
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