ST7MC1K2-Auto datasheet(120/371 Pages) STMICROELECTRONICS

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Table 50.

CR1 register description

Bit Name

Function

ICIE

Input capture interrupt enable

0: Interrupt is inhibited

1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is

set

6OCIE

Output compare interrupt enable

0: Interrupt is inhibited

1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is

set

5TOIE

Timer overflow interrupt enable

0: Interrupt is inhibited

1: A timer interrupt is enabled whenever the TOF bit of the SR register is set

4FOLV2

Forced output compare 2

This bit is set and cleared by software.

0: No effect on the OCMP2 pin

1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and

even if there is no successful comparison

3FOLV1

Forced output compare 1

This bit is set and cleared by software.

0: No effect on the OCMP1 pin

1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if

there is no successful comparison

2OLVL2

Output level 2

This bit is copied to the OCMP2 pin whenever a successful comparison occurs with

the OC2R register and OCxE is set in the CR2 register. This value is copied to the

OCMP1 pin in one pulse mode and pulse width modulation mode.

1IEDG1

Input edge 1

This bit determines which type of level transition on the ICAP1 pin triggers the

capture.

0: A falling edge triggers the capture

1: A rising edge triggers the capture

0OLVL1

Output level 1

The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs

with the OC1R register and the OC1E bit is set in the CR2 register.

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