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ST7MC1K2-Auto 数据表(PDF) 123 Page - STMicroelectronics |
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ST7MC1K2-Auto 数据表(HTML) 123 Page - STMicroelectronics |
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123 / 371 page  Obsolete Product(s) - Obsolete Product(s) ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto On-chip peripherals 123/371 Input capture 1 high register (IC1HR) This is an 8-bit read-only register that contains the high part of the counter value (transferred by the input capture 1 event). Input capture 1 low register (IC1LR) This is an 8-bit read-only register that contains the low part of the counter value (transferred by the input capture 1 event). Output compare 1 high register (OC1HR) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 3OCF2 Output compare flag 2 0: No match (reset value) 1: The content of the free running counter has matched the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register. 2TIMD Timer disable This bit is set and cleared by software. When set, it freezes the timer prescaler and counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce power consumption. Access to the timer registers is still available, allowing the timer configuration to be changed while it is disabled. 0: Timer enabled 1: Timer prescaler, counter and outputs disabled 1:0 - Reserved, must be kept cleared IC1HR Reset value: undefined 7 654 32 10 MSB LSB RO RO RO RO RO RO RO RO IC1LR Reset value: undefined 7 654 32 10 MSB LSB RO RO RO RO RO RO RO RO OC1HR Reset value: 1000 0000 (80h) 7 654 32 10 MSB LSB R/W R/W R/W R/W R/W R/W R/W R/W Table 52. CSR register description (continued) Bit Name Function Obsolete Product(s) - Obsolete Product(s) |
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