ST7MC1K2-Auto datasheet(137/371 Pages) STMICROELECTRONICS

137 / 371 page

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ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto

On-chip peripherals

137/371

SPI control/status register (SPICSR)

4MSTR

Master mode

This bit is set and cleared by software. It is also cleared by hardware when, in

master mode, SS = 0 (see Master mode fault (MODF) on page 133).

0: Slave mode

1: Master mode. The function of the SCK pin changes from an input to an output

and the functions of the MISO and MOSI pins are reversed.

3CPOL

Clock polarity

This bit is set and cleared by software. This bit determines the idle state of the

serial clock. The CPOL bit affects both the master and slave modes.

0: SCK pin has a low level idle state

1: SCK pin has a high level idle state

Note: If CPOL is changed at the communication byte boundaries, the SPI must be

disabled by resetting the SPE bit.

2CPHA

Clock phase

This bit is set and cleared by software.

0: The first clock transition is the first data capture edge

1: The second clock transition is the first capture edge

Note: The slave must have the same CPOL and CPHA settings as the master.

1:0 SPR[1:0]

Serial clock frequency

These bits are set and cleared by software. Used with the SPR2 bit, they select the

baud rate of the SPI serial clock SCK output by the SPI in master mode.

Note: These 2 bits have no effect in slave mode.

SPICSR

Reset value: 0000 0000 (00h)

654

SPIF

WCOL

OVR

MODF

Reserved

SOD

SSM

SSI

R/W

Table 57.

SPICSR register description

Bit Name

Function

SPIF

Serial peripheral data transfer flag

This bit is set by hardware when a transfer has been completed. An interrupt is

generated if SPIE = 1 in the SPICR register. It is cleared by a software sequence (an

access to the SPICSR register followed by a write or a read to the SPIDR register).

0: Data transfer is in progress or the flag has been cleared

1: Data transfer between the device and an external device has been completed

Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the

SPICSR register is read.

6WCOL

Write collision status

This bit is set by hardware when a write to the SPIDR register is done during a

transmit sequence. It is cleared by a software sequence (see Figure 59).

0: No write collision occurred

1: A write collision has been detected

Table 56.

SPICR register description (continued)

Bit

Name

Function

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