ST7MC1K2-Auto datasheet(138/371 Pages) STMICROELECTRONICS

138 / 371 page

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SPI data I/O register (SPIDR)

The SPIDR register is used to transmit and receive data on the serial bus. In a master

device, a write to this register initiates the transmission/reception of another byte.

Note:

During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift

buffer is actually being read.

5OVR

SPI overrun error

This bit is set by hardware when the byte currently being received in the shift register

is ready to be transferred into the SPIDR register while SPIF = 1 (see Overrun

condition (OVR) on page 133). An interrupt is generated if SPIE = 1 in the SPICR

0: No overrun error

1: Overrun error detected

4MODF

Mode fault flag

This bit is set by hardware when the SS pin is pulled low in master mode (see Master

mode fault (MODF) on page 133). An SPI interrupt can be generated if SPIE = 1 in

the SPICR register. This bit is cleared by a software sequence (an access to the

SPICSR register while MODF = 1 followed by a write to the SPICR register).

0: No master mode fault detected

1: A fault in master mode has been detected

Reserved, must be kept cleared

2SOD

SPI output disable

This bit is set and cleared by software. When set, it disables the alternate function of

the SPI output (MOSI in master mode/MISO in slave mode).

0: SPI output enabled (if SPE = 1)

1: SPI output disabled

SSM

SS management

This bit is set and cleared by software. When set, it disables the alternate function of

the SPI SS pin and uses the SSI bit value instead (see Slave select management on

page 129).

0: Hardware management (SS managed by external pin)

1: Software management (internal SS signal controlled by SSI bit. External SS pin

free for general-purpose I/O)

SSI

SS internal mode

This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the level

of the SS slave select signal when the SSM bit is set.

0: Slave selected

1: Slave deselected

SPIDR

Reset value: undefined

654

D[7:0]

R/W

Table 57.

SPICSR register description (continued)

Bit Name

Function

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