ST7MC1K2-Auto datasheet(145/371 Pages) STMICROELECTRONICS

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The TDRE bit is set by hardware and it indicates that:

●

the TDR register is empty,

●

the data transfer is beginning,

●

the next data can be written in the SCIDR register without overwriting the previous

data.

This flag generates an interrupt if the TIE bit is set and the I[|1:0] bits are cleared in the CCR

When a transmission is taking place, a write instruction to the SCIDR register stores the

data in the TDR register and which is copied in the shift register at the end of the current

transmission.

When no transmission is taking place, a write instruction to the SCIDR register places the

data directly in the shift register, the data transmission starts, and the TDRE bit is

immediately set.

When a character transmission is complete (after the stop bit) the TC bit is set and an

interrupt is generated if the TCIE is set and the I[1:0] bits are cleared in the CCR register.

Clearing the TC bit is performed by the following software sequence:

Accessing the SCISR register.

Writing to the SCIDR register.

Note:

The TDRE and TC bits are cleared by the same software sequence.

Break characters

Setting the SBK bit loads the shift register with a break character. The break character

length depends on the M bit (see Figure 62).

As long as the SBK bit is set, the SCI sends break characters to the TDO pin. After clearing

this bit by software, the SCI inserts a logic 1 bit at the end of the last break character to

guarantee the recognition of the start bit of the next character.

Idle line

Setting the TE bit drives the SCI to send a preamble of 10 (M = 0) or 11 (M = 1) consecutive

‘1’s (idle line) before the first character.

In this case, clearing and then setting the TE bit during a transmission sends a preamble

(idle line) after the current word. Note that the preamble duration (10 or 11 consecutive ‘1’s

depending on the M bit) does not take into account the stop bit of the previous character.

Note:

Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the

best time to toggle the TE bit is when the TDRE bit is set, that is, before writing the next byte

in the SCIDR.

Receiver

The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9

bits and the MSB is stored in the R8 bit in the SCICR1 register.

Character reception

During a SCI reception, data shifts in least significant bit first through the RDI pin. In this

mode, the SCIDR register consists or a buffer (RDR) between the internal bus and the

received shift register (see Figure 61).

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