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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST7MC1K2-Auto 数据表(PDF) 147 Page - STMicroelectronics |
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ST7MC1K2-Auto 数据表(HTML) 147 Page - STMicroelectronics |
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147 / 371 page  Obsolete Product(s) - Obsolete Product(s) ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto On-chip peripherals 147/371 Framing error A framing error is detected when: ● The stop bit is not recognized on reception at the expected time, following either a desynchronization or excessive noise. ● A break is received. When the framing error is detected: ● the FE bit is set by hardware ● Data is transferred from the shift register to the SCIDR register. ● No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The FE bit is reset by a SCISR register read operation followed by a SCIDR register read operation. Break character When a break character is received, the SCI handles it as a framing error. To differentiate a break character from a framing error, it is necessary to read the SCIDR. If the received value is 00h, it is a break character. Otherwise it is a framing error. Conventional baud rate generation The baud rates for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows: Equation 7 where PR = 1, 3, 4 or 13 (see SCI baud rate register (SCIBRR) on page 156, SCP[1:0] bits) TR = 1, 2, 4, 8, 16, 32, 64,128 (see SCI baud rate register (SCIBRR) on page 156, SCT[2:0] bits) RR = 1, 2, 4, 8, 16, 32, 64,128 (see SCI baud rate register (SCIBRR) on page 156, SCR[2:0] bits) Example: If fCPU is 8 MHz (normal mode) and if PR = 13 and TR = RR = 1, the transmit and receive baud rates are 38400 baud. Note: The baud rate registers MUST NOT be changed while the transmitter or the receiver is enabled. Extended baud rate generation The extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescaler, whereas the conventional baud rate generator retains industry standard software compatibility. The extended baud rate generator block diagram is described in Figure 63. The output clock rate sent to the transmitter or to the receiver is the output from the 16 divider divided by a factor ranging from 1 to 255 set in the SCIERPR or the SCIETPR registers. Tx = (16*PR)*TR fCPU Rx = (16*PR)*RR fCPU Obsolete Product(s) - Obsolete Product(s) |
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