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DS31256 数据表(PDF) 125 Page - Maxim Integrated Products |
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DS31256 数据表(HTML) 125 Page - Maxim Integrated Products |
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125 / 183 page  DS31256 256-Channel, High-Throughput HDLC Controller 125 of 183 9.3.5 DMA Configuration RAM The device contains an on-board set of 1536 dwords (6 dwords per channel times 256 channels) that are used by the host to configure the DMA and used by the DMA to store values locally when it is processing a packet. Most of the fields within the DMA configuration RAM are for DMA use and the host never writes to these fields. The host is only allowed to write (configure) to the lower word of dword 1 for each HDLC channel. In Figure 9-21, the host-configurable fields are denoted with a thick box. Figure 9-21. Transmit DMA Configuration RAM dmatcram msb 31 lsb 0 Transmit DMA Configuration RAM 000h 004h 008h HDLC Channel 1 00Ch 010h 014h HDLC Channel 256 Fields shown within the thick box are written by the Host; all other fields are for usage by the DMA and can only be read by the Host Next Descriptor Pointer (16) Next Priority Pending Descriptor Pointer (16) Byte Count (13) Current Packet Data Buffer Address (32) Start Descriptor Pointer (16) CH EN Last Pending Descriptor Pointer (16) Next Pending Descriptor Pointer (16) Next Priority Descriptor Pointer (16) Last Priority Pending Descriptor Pointer (16) DQS unused (16) EOF CV PEND ST(2) PRI ST(2) unused (9) 17D8h 17DCh 17F0h 17F4h 17F8h 17FCh PPP un- used Next Descriptor Pointer (16) Next Priority Pending Descriptor Pointer (16) Byte Count (13) Current Packet Data Buffer Address (32) Start Descriptor Pointer (16) CH EN Last Pending Descriptor Pointer (16) Next Pending Descriptor Pointer (16) Next Priority Descriptor Pointer (16) Last Priority Pending Descriptor Pointer (16) DQS unused (16) EOF CV PEND ST(2) PRI ST(2) unused (9) PPP un- used |
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