DS31256 datasheet(126/183 Pages) MAXIM

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DS31256 256-Channel, High-Throughput HDLC Controller

126 of 183

- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -

dword 0; Bits 0 to 31/Current Data Buffer Address. This is the current 32-bit address of the data buffer that is

being used. This address is used by the DMA to keep track of where data should be read from as it is passed to the

transmit FIFO.

- HOST MUST CONFIGURE -

dword 1; Bit 0/Channel Enable (CHEN). This bit is controlled by both the host and the transmit DMA to enable

and disable a HDLC channel. The DMA automatically disables a channel when an error condition occurs (see

Section 9.2.1 for a discussion on error conditions). The DMA automatically enables a channel when it detects that

the channel reset (CHRST) bit in the pending-queue descriptor is set to 1.

0 = HDLC channel disabled

1 = HDLC channel enabled

- HOST MUST CONFIGURE -

dword 1; Bit 1/Done-Queue Select (DQS). This bit determines whether the transmit DMA writes to the done

queue only after a complete HDLC packet (which may be only a single buffer) has been transmitted (in which case

the descriptor pointer in the done queue corresponds to the first descriptor of the packet) or whether it should write

to the done queue after each data buffer has been transmitted (in which case the descriptor pointer in the done

queue corresponds to a single data buffer). The setting of this bit also affects the reporting of the status field in the

transmit done queue. When DQS = 0, the only nonerrored status possible is a setting of 000. When DQS = 1, then

the nonerrored settings of 001, 010, and 011 are possible.

0 = write to the done queue only after a complete HDLC packet has been transmitted

1 = write to the done queue after each data buffer is transmitted

- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -

dword 1; Bit 2/Unused. This field is not used by the DMA and could be any value when read.

- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -

dword 1; Bits 3 to 15/Byte Count. The DMA uses these 13 bits to keep track of the number of bytes stored in the

data buffer. Maximum is 8188 Bytes (0000h = 0 Bytes / 1FFCh = 8188 Bytes).

- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -

dword 1; Bit 16/Chain Valid (CV). This is an internal copy of the CV field that resides in the current packet

descriptor that the DMA is operating on. See Section 9.2.2 for more details on the CV bit.

- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -

dword 1; Bit 17/End of Frame (EOF). This is an internal copy of the EOF field that resides in the current Packet

Descriptor that the DMA is operating on. See Section 9.2.2 for more details about the EOF bit.

- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -

dword 1; Bits 18 to 19/Pending State (PENDST). This field is used by the transmit DMA to keep track of

queued descriptors as they arrive from the pending queue and for the DMA to know when it should create a

horizontal linked list of transmit descriptors and where it can find the next valid descriptor. This field handles

standard packets and the PRIST field handles priority packets.

State

Next Descriptor Pointer Field

Next Pending Descriptor Pointer Field

Not Valid

Valid

Not Valid

Valid

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