DS31256 datasheet(128/183 Pages) MAXIM

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DS31256 256-Channel, High-Throughput HDLC Controller

128 of 183

- FOR DMA USE ONLY/HOST CAN ONLY READ THIS FIELD -

dword 5; Bits 16 to 31/Next Priority Pending Descriptor Pointer. This 16-bit value is the offset from the

transmit descriptor base address of the first transmit priority packet descriptor for the packet priority that is queued

up next for transmission.

TDMACIS

Transmit DMA Configuration Indirect Select

0870h

Bit #

Name

HCID7

HCID6

HCID5

HCID4

HCID3

HCID2

HCID1

HCID0

Default

Bit #

Name

IAB

IARW

n/a

TDCW3

TDCW2

TDCW1

TDCW0

Default

Note: Bits that are underlined are read-only; all other bits are read-write.

Bits 0 to 7/HDLC Channel ID (HCID0 to HCID7)

00000000 (00h) = HDLC channel number 1

11111111 (FFh) = HDLC channel number 256

Bits 8 to 11/Transmit DMA Configuration RAM Word Select Bits 0 to 3 (TDCW0 to TDCW3)

0000 = lower word of dword 0

0001 = upper word of dword 0

0010 = lower word of dword 1 (only word that the host can write to)

0011 = upper word of dword 1

0100 = lower word of dword 2

0101 = upper word of dword 2

0110 = lower word of dword 3

0111 = upper word of dword 3

1000 = lower word of dword 4

1001 = upper word of dword 4

1010 = lower word of dword 5

1011 = upper word of dword 5

Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal transmit DMA

configuration RAM, the host should write this bit to 1. This causes the device to begin obtaining the data from the

channel location indicated by the HCID bits. During the read access, the IAB bit is set to 1. Once the data is ready

to be read from the TDMAC register, the IAB bit is set to 0. When the host wishes to write data to the internal

transmit DMA configuration RAM, this bit should be written to 0 by the host. This causes the device to take the

data that is currently present in the TDMAC register and write it to the channel location indicated by the HCID

bits. When the device has completed the write, the IAB bit is set to 0.

Bit 15/Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read-only bit is set

to 1. During a read operation, this bit is set to 1 until the data is ready to be read. It is set to 0 when the data is

ready to be read. During a write operation, this bit is set to 1 while the write is taking place. It is set to 0 once the

write operation has completed.

DS31256 数据表(PDF) 128 Page - Maxim Integrated Products

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