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DS31256 数据表(PDF) 129 Page - Maxim Integrated Products |
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DS31256 数据表(HTML) 129 Page - Maxim Integrated Products |
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129 / 183 page ![]() DS31256 256-Channel, High-Throughput HDLC Controller 129 of 183 Register Name: TDMAC Register Description: Transmit DMA Configuration Register Address: 0874h Bit # 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 Default 0 0 0 0 0 0 0 0 Bit # 15 14 13 12 11 10 9 8 Name D15 D14 D13 D12 D11 D10 D9 D8 Default 0 0 0 0 0 0 0 0 Note: Bits that are underlined are read only, all other bits are read-write. Bits 0 to 15/Transmit DMA Configuration RAM Data (D0 to D15). Data that is written to or read from the transmit DMA configuration RAM. |
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