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DS31256 数据表(PDF) 170 Page - Maxim Integrated Products

部件名 DS31256
功能描述  256-Channel, High-Throughput HDLC Controller
PDF  183 Pages
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制造商  MAXIM [Maxim Integrated Products]
网页  https://www.maximintegrated.com/en.html
标志 MAXIM - Maxim Integrated Products

DS31256 数据表(HTML) 170 Page - Maxim Integrated Products

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DS31256 256-Channel, High-Throughput HDLC Controller
170 of 183
AC CHARACTERISTICS: LOCAL BUS IN BRIDGE MODE (LMS = 0)
(VDD = 3.0V to 3.6V, TA = 0°C to +70°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Delay Time from the Rising Edge of PCLK
to Output Valid from Tri-state
t1
7
17
ns
Delay Time from the Rising Edge of PCLK
to Tri-State from Output Valid
t2
7
15
ns
Delay Time from the Rising Edge of PCLK
to Output Valid from an Already Active
Drive State
t3
6
14
ns
LD[15:0] Setup Time to the Rising Edge of
PCLK
t4
1
ns
LD[15:0] Hold Time from the Rising Edge
of PCLK
t5
5
ns
Input Setup Time to the Rising Edge of
PCLK
t6
1
ns
Input Hold Time from the Rising Edge of
PCLK
t7
5
ns
Delay Time from the Rising Edge of PCLK
to the Rising Edge of LCLK
t8
4
7
ns
Delay Time from the Falling Edge of
PCLK to the Falling Edge of LCLK
t9
5
8
ns
Figure 13-2. Local Bus Bridge Mode (LMS = 0) AC Timing Diagram
Data Valid
PCLK
LINT, LRDY
LHLDA (
LBG)
LD[15:0]
LA[19:0],
LWR (LR/W),
LRD (LDS), LBHE
LA[19:0], LD[15:0],
LBHE,
LWR (LR/W), LRD (DS)
Data Valid
Tri-state
Data Valid
LA[19:0],
LWR (LR/W),
LRD (DS), LHOLD (LBR),
LBGACK
t8
LCLK
t9
Tri-state
t3
t5
t4
t6
t7
t2
t1



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