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AM186ED-20KC/W 数据表(PDF) 24 Page - Advanced Micro Devices |
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AM186ED-20KC/W 数据表(HTML) 24 Page - Advanced Micro Devices |
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24 / 88 page  24 Am186ED/EDLV Microcontrollers PRELI M INARY D RA F T refresh requests in priority of activity requests received by the processor. For more information, see the HLDA pin description on page 23. INT0 Maskable Interrupt Request 0 (input, asynchronous) This pin indicates to the microcontroller that an interrupt request has occurred. If the INT0 pin is not masked, the microcontroller transfers program execution to the location specified by the INT0 vector in the microcontroller interrupt vector table. Interrupt requests are synchronized internally and can be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must co ntin ue as se r t i ng INT0 u n ti l the r e q ues t is acknowledged. INT1/SELECT Maskable Interrupt Request 1 (input, asynchronous) Slave Select (input, asynchronous) INT1—This pin indicates to the microcontroller that an interrupt request has occurred. If INT1 is not masked, the microcontroller transfers program execution to the lo c a tio n s pec if ied by the INT1 v e c t or i n the microcontroller interrupt vector table. Interrupt requests are synchronized internally and can be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must co ntin ue as se r t i ng INT1 u n ti l the r e q ues t is acknowledged. SELECT—When the microcontroller interrupt control unit is operating as a slave to an external interrupt controller, this pin indicates to the microcontroller that an interrupt type appears on the address and data bus. The INT0 pin must indicate to the microcontroller that an interrupt has occurred before the SELECT pin indicates to the microcontroller that the interrupt type appears on the bus. INT2/INTA0/PWD/PIO31 Maskable Interrupt Request 2 (input, asynchronous) Interrupt Acknowledge 0 (output, synchronous) Pulse Width Demodulator (input, Schmitt trigger) INT2—This pin indicates to the microcontroller that an interrupt request has occurred. If the INT2 pin is not masked, the microcontroller transfers program execution to the location specified by the INT2 vector in the microcontroller interrupt vector table. Interrupt requests are synchronized internally and can be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must co ntin ue as s e r t ing IN T 2 unti l the r e q ues t is acknowledged. INT2 becomes INTA0 when INT0 is configured in cascade mode. INTA0—When the microcontroller interrupt control unit is operating in cascade mode, this pin indicates to the system that the microcontroller needs an interrupt type to process the interrupt request on INT0. Th e peripheral issuing the interrupt request must provide the microcontroller with the corresponding interrupt type. PWD—If pulse width demodulation is enabled, PWD processes a signal through the Schmitt trigger. PWD is used internally to drive TIMERIN0 and INT2, and PWD is inverted internally to drive TIMERIN1 and INT4. If INT2 and INT4 are enabled and timer 0 and timer 1 are properly configured, the pulse width of the alternating PWD signal can be calculated by comparing the values in timer 0 and timer 1. In PW D mo de, th e s i gn al s TIM ER I N0 /P IO 11 , TIMERIN1/PIO0, and INT4/PIO30 can be used as PIOs. If they are not used as PIOs, they are ignored internally. The level of INT2/INTA0/PWD/PIO31 is reflected in the PIO data register for PIO31 as if it was a PIO. INT3/INTA1/IRQ Maskable Interrupt Request 3 (input, asynchronous) Interrupt Acknowledge 1 (output, synchronous) Slave Interrupt Request (output, synchronous) INT3—This pin indicates to the microcontroller that an interrupt request has occurred. If the INT3 pin is not masked, the microcontroller then transfers program execution to the location specified by the INT3 vector in the microcontroller interrupt vector table. Interrupt requests are synchronized internally, and can be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must co ntin ue as s e r t ing IN T 3 unti l the r e q ues t is acknowledged. INT3 becomes INTA1 when INT1 is configured in cascade mode. INTA1—When the microcontroller interrupt control unit is operating in cascade mode, this pin indicates to the system that the microcontroller needs an interrupt type to process the interrupt request on INT1. Th e peripheral issuing the interrupt request must provide the microcontroller with the corresponding interrupt type. IRQ—When the microcontroller interrupt control unit is operating as a slave to an external master interrupt controller, this pin lets the microcontroller issue an interrupt request to the external master interrupt controller. |
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