AM186ED-20KCSLASHW datasheet(41/88 Pages) AMD

41 / 88 page

Am186ED/EDLV Microcontrollers

PRELI M INARY

F T

External Source Clock

Alternately, the internal oscillator can be driven from an

external clock source. This source should be con-

nected to the input of the inverting amplifier (X1), with

the output (X2) not connected.

System Clocks

The base system clock of AMD’s original 80C186 and

80C188 microcontrollers is renamed CLKOUTA and

the additional output is called CLKOUTB. CLKOUTA

and CLKOUTB operate at either the processor fre-

quency or the PLL frequency. The output drivers for

both clocks are individually programmable for disable.

Figure 9 shows the organization of the clocks.

The second clock output (CLKOUTB) allows one clock

to run at the PLL frequency and the other clock to run

at the power-save frequency. Individual drive enable

bits allow selective enabling of just one or both of these

clock outputs.

Power-Save Operation

The power-save mode of the Am186ED/EDLV micro-

controllers reduces power consumption and heat dissi-

pation, thereby extending battery life in portable

systems. In power-save mode, operation of the CPU

and internal peripherals continues at a slower clock fre-

quency. When an interrupt occurs, the microcontroller

automatically returns to its normal operating frequency

on the internal clock’s next rising edge of t3.

Note: Power-save operation requires that clock-de-

pendent devices be reprogrammed for clock frequency

changes. Software drivers must be aware of clock fre-

quency. The power-save divisor should not be set to

operate the processor core below 100 kHz.

Initialization and Processor Reset

Processor initialization or startup is accomplished by

driving the RES input pin Low. RES must be held Low

for 1 ms during power-up to ensure proper device ini-

tialization. RES forces the Am186ED/EDLV microcon-

trollers to terminate all execution and local bus activity.

No instruction or bus activity occurs as long as RES is

active. After RES becomes inactive and an internal

processing interval elapses, the microcontroller begins

execution with the instruction at physical location

FFFF0h, with UCS asserted with three wait states.

RES also sets some registers to predefined values and

resets the watchdog timer.

Reset Configuration Register

When the RES input is asserted Low, the contents of

the address/data bus (AD15–AD0) are written into the

reset configuration register. The system can place con-

figuration information on the address/data bus using

weak external pullup or pulldown resistors, or using an

external driver that is enabled during reset. The pro-

cessor does not drive the address/data bus during re-

set.

For example, the reset configuration register could be

used to provide the software with the position of a con-

figuration switch in the system. Using weak external

pullup and pulldown resistors on the address and data

bus, the system can provide the microcontroller with a

value corresponding to the position of the jumper dur-

ing a reset.

Figure 9.

Clock Organization

PLL

X1, X2

CLKDIV2

Processor Clock

PSEN

CAD

CAF

CBF

CBD

CLKOUTB

CLKOUTA

Mux

Time

Delay

6 ns ±

Power-Save

Divisor

/1 to /128

Note: For frequencies under 16 MHz, use PLL bypass.

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