AM186ED-20KCSLASHW datasheet(31/88 Pages) AMD

31 / 88 page

Am186ED/EDLV Microcontrollers

PRELI M INARY

F T

microcontroller, tie SRDY High. If the system does not

use SRDY, tie the pin Low to yield control to ARDY.

TMRIN0/PIO11

Timer Input 0 (input, synchronous, edge-sensitive)

This pin supplies a clock or control signal to the internal

microcontroller timer 0. After internally synchronizing a

Low-to-High transition on TMRIN0, the microcontroller

increments the timer. TMRIN0 must be tied High if not

being used. When PIO11 is enabled, TMRIN0 is pulled

High internally.

TMRIN0 is driven internally by INT2/INTA0/PWD when

pulse width demodulation mode is enabled. The

TMRIN0/PIO11 pin can be used as a PIO when pulse

width demodulation mode is enabled.

TMRIN1/PIO0

Timer Input 1 (input, synchronous, edge-sensitive)

This pin supplies a clock or control signal to the internal

microcontroller timer 1. After internally synchronizing a

Low-to-High transition on TMRIN1, the microcontroller

increments the timer. TMRIN1 must be tied High if not

being used. When PIO0 is enabled, TMRIN1 is pulled

High internally.

TMRIN1 is driven internally by INT2/INTA0/PWD when

pulse width demodulation mode is enabled. The

TMRIN1/PIO0 pin can be used as a PIO when pulse

width demodulation mode is enabled.

TMROUT0/PIO10

Timer Output 0 (output, synchronous)

This pin supplies the system with either a single pulse

or a continuous waveform with a programmable duty

cycle. TMROUT0 is floated during a bus hold or reset.

TMROUT1/PIO1

Timer Output 1 (output, synchronous)

This pin supplies the system with either a single pulse

or a continuous waveform with a programmable duty

cycle. TMROUT1 floats during a bus hold or reset.

TXD0/PIO22

Transmit Data 0 (output, asynchronous)

This pin supplies asynchronous serial transmit data to

the system from serial port 0.

TXD1/PIO27

Transmit Data 1 (output, asynchronous)

This pin supplies asynchronous serial transmit data to

the system from serial port 1.

UCS/ONCE1

Upper Memory Chip Select (output, synchronous)

ONCE Mode Request 1 (input, internal pullup)

UCS—This pin indicates to the system that a memory

access is in progress to the upper memory block. The

base address and size of the upper memory block are

programmable up to 512 Kbytes.

UCS is three-stated and held resistively High during a

bus hold condition. In addition, UCS has an ~9-kohm

internal pullup resistor that is active during reset.

After reset, UCS is active for the 64 Kbyte memory

range from F0000h to FFFFFh, including the reset

address of FFFF0h.

When RAS1 is activated, the code activating RAS1

must not reside in the UCS memory block. When RAS1

is activated, UCS is automatically deactivated and

remains negated. This allows code to boot from UCS,

copy its code to another memory device, then activate

a DRAM bank in place of the UCS memory block.

ONCE1—During reset, this pin and LCS/ONCE0 indi-

cate to the microcontroller the mode in which it should

operate. ONCE0 and ONCE1 are sampled on the ris-

ing edge of RES. If both pins are asserted Low, the mi-

crocontroller enters ONCE mode. Otherwise, it

operates normally. In ONCE mode, all pins assume a

high-impedance state and remain in that state until a

subsequent reset occurs. To guarantee that the micro-

controller does not inadvertently enter ONCE mode,

ONCE1 has a weak internal pullup resistor that is ac-

tive only during a reset.

UZI/PIO26

Upper Zero Indicate (output, synchronous)

This pin lets the designer determine if an access to the

interrupt vector table is in progress by ORing it with bits

15–10 of the address and data bus (AD15–AD10). UZI

is the logical AND of the inverted A19–A16 bits. It asserts

in the first period of a bus cycle and is held throughout the

cycle.

VCC

Power Supply (input)

These pins supply power (+5 V) to the microcontroller.

WHB

Write High Byte (output, three-state, synchronous)

This pin and WLB indicate to the system which bytes of

the data bus (upper, lower, or both) participate in a write

cycle. In 80C186 microcontroller designs, information

is provided by BHE, AD0, and WR. However, by using

WHB and WLB, the standard system interface logic

and external address latch that were required are

eliminated.

AM186ED-20KC/W 数据表(PDF) 31 Page - Advanced Micro Devices

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