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AM186ED-20KC/W 数据表(PDF) 82 Page - Advanced Micro Devices |
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AM186ED-20KC/W 数据表(HTML) 82 Page - Advanced Micro Devices |
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82 / 88 page  82 Am186ED/EDLV Microcontrollers PRELI M INARY D RA F T SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges Ready and Peripheral (20 MHz and 25 MHz) Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL=0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V. a This timing must be met to guarantee proper operation. b This timing must be met to guarantee recognition at the clock edge. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Ready and Peripheral (33 MHz and 40 MHz) Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL=0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V. a This timing must be met to guarantee proper operation. b This timing must be met to guarantee recognition at the clock edge. Parameter Preliminary Preliminary Unit 20 MHz 25 MHz No. Symbol Description Min Max Min Max Ready and Peripheral Timing Requirements 47 tSRYCL SRDY Transition Setup Time(a) 10 10 ns 48 tCLSRY SRDY Transition Hold Time(a) 33 ns 49 tARYCH ARDY Resolution Transition Setup Time(b) 10 10 ns 50 tCLARX ARDY Active Hold Time(a) 44 ns 51 tARYCHL ARDY Inactive Holding Time 6 6 ns 52 tARYLCL ARDY Setup Time(a) 15 15 ns 53 tINVCH Peripheral Setup Time(b) 10 10 ns 54 tINVCL DRQ Setup Time(b) 10 10 ns Peripheral Timing Responses 55 tCLTMV Timer Output Delay 25 20 ns Parameter Preliminary Unit 33 MHz 40 MHz No. Symbol Description Min Max Min Max Ready and Peripheral Timing Requirements 47 tSRYCL SRDY Transition Setup Time(a) 85 ns 48 tCLSRY SRDY Transition Hold Time(a) 32 ns 49 tARYCH ARDY Resolution Transition Setup Time(b) 85 ns 50 tCLARX ARDY Active Hold Time(a) 43 ns 51 tARYCHL ARDY Inactive Holding Time 6 5 ns 52 tARYLCL ARDY Setup Time(a) 10 5 ns 53 tINVCH Peripheral Setup Time(b) 85 ns 54 tINVCL DRQ Setup Time(b) 85 ns Peripheral Timing Responses 55 tCLTMV Timer Output Delay 15 12 ns |
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