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AM186ED-20KC/W 数据表(PDF) 77 Page - Advanced Micro Devices

部件名 AM186ED-20KC/W
功能描述  High Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers
PDF  88 Pages
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制造商  AMD [Advanced Micro Devices]
网页  http://www.amd.com
标志 AMD - Advanced Micro Devices

AM186ED-20KC/W 数据表(HTML) 77 Page - Advanced Micro Devices

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Am186ED/EDLV Microcontrollers
77
PRELI M INARY
D
RA
F T
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
Software Halt Cycle (20 MHz and 25 MHz)
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL =50 pF. For switching tests, VIL=0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V.
a
Testing is performed with equal loading on referenced pins.
b
This parameter applies to the DEN signal.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges
Software Halt Cycle (33 MHz and 40 MHz)
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL =50 pF. For switching tests, VIL=0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V.
a
Testing is performed with equal loading on referenced pins.
b
This parameter applies to the DEN signal.
Parameter
Preliminary
Unit
20 MHz
25 MHz
No.
Symbol
Description
Min
Max
Min
Max
General Timing Responses
3tCHSV
Status Active Delay
0
25
0
20
ns
4tCLSH
Status Inactive Delay
0
25
0
20
ns
5tCLAV
AD Address Invalid Delay and BHE
0
25
0
20
ns
9tCHLH
ALE Active Delay
25
20
ns
10
tLHLL
ALE Width
tCLCL–10=40
tCLCL–10=30
ns
11
tCHLL
ALE Inactive Delay
25
20
ns
19
tDXDL
DEN Inactive to DT/R Low(a)
00
ns
22
tCHCTV
Control Active Delay 2(b)
0250
20
ns
68
tCHAV
CLKOUTA High to A Address Invalid
0
25
0
20
ns
Parameter
Preliminary
Unit
33 MHz
40 MHz
No.
Symbol
Description
Min
Max
Min
Max
General Timing Responses
3tCHSV
Status Active Delay
0
15
0
12
ns
4tCLSH
Status Inactive Delay
0
15
0
12
ns
5tCLAV
AD Address Invalid Delay and BHE
0
15
0
12
ns
9tCHLH
ALE Active Delay
15
12
ns
10
tLHLL
ALE Width
tCLCL–10=20
tCLCL–5=20
ns
11
tCHLL
ALE Inactive Delay
15
12
ns
19
tDXDL
DEN Inactive to DT/R Low(a)
00
ns
22
tCHCTV
Control Active Delay 2(b)
015012
ns
68
tCHAV
CLKOUTA High to A Address Invalid
0
15
0
10
ns



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