AM186ED-20KCSLASHW datasheet(36/88 Pages) AMD

36 / 88 page

Am186ED/EDLV Microcontrollers

PRELI M INARY

F T

Figure 7.

8-Bit Mode—Read and Write with Address Bus Disable in Effect

BUS INTERFACE UNIT

The bus interface unit controls all accesses to external

peripherals and memory devices. External accesses

include those to memory devices, as well as those to

memory-mapped and I/O-mapped peripherals and the

peripheral control block. The Am186ED/EDLV micro-

controllers provide an enhanced bus interface unit with

the following features:

n A nonmultiplexed address bus

n DRAM address multiplexing

n A static bus-sizing option for 8-bit and 16-bit mem-

ory and I/O

n Separate byte write enables and CAS for High and

Low bytes

n Data strobe bus interface option

The standard 80C186/188 microcontroller multiplexed

address and data bus requires system interface logic

and an external address latch. On the Am186ED/EDLV

microcontrollers, new byte write enables, DRAM con-

trol logic, and a new nonmultiplexed address bus can

reduce design costs by eliminating this external logic.

The standard 80C186/188 microcontroller required ex-

ternal DRAM controller logic and DRAM address multi-

plex circuitry fo r in terf acing to DRAM . On the

Am186ED/EDLV microcontrollers, the integrated

DRAM controller and internal address multiplexing can

reduce design costs by eliminating this external logic.

Further, system costs can be reduced for systems

using more than 64K of RAM by replacing SRAM with

less expensive DRAM.

Nonmultiplexed Address Bus

The nonmultiplexed address bus (A19–A0) is valid

one-half CLKOUTA cycle in advance of the address on

the AD bus. When used in conjunction with the modi-

fied UCS and LCS outputs and the byte-write enable

signals, the A19–A0 bus provides a seamless interface

to SRAM, and Flash EPROM memory systems.

DRAM Address Multiplexing

The A19–A0 address bus also provides the addresses

for the DRAM. When RAS0 or RAS1 asserts for a read

or write, all the address signals are valid. This allows

the DRAM to latch the odd addresses into the row ad-

dress. Before the UCAS and/or LCAS asserts, the odd

addresses A17–A1 change to reflect the even ad-

dresses. This allows the DRAM to latch in the even ad-

dresses into the column address. During a refresh

cycle, the entire A19–A0 address bus is stable but un-

defined. The internal address and that reflected on the

AD bus is all 1s. The DRAM pin interface is shown in

Table 6.

CLKOUTA

AD7–AD0

(Read)

Address

AD15–AD8

LCS, or UCS

AD7–AD0

(Write)

Data

Address

Phase

Data

Phase

A19–A0

MCSx, PCSx

Address

Data

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