AM186ED-20KCSLASHW datasheet(47/88 Pages) AMD

47 / 88 page

Am186ED/EDLV Microcontrollers

PRELI M INARY

F T

Figure 10.

DMA Unit Block Diagram

DMA Channel Control Registers

Each DMA control register determines the mode of op-

eration for the particular DMA channel. The DMA con-

trol registers specify the following:

n The mode of synchronization

n Whether bytes or words are transferred

n Whether an interrupt is generated after the last

transfer

n Whether the DRQ pins are configured as INT pins

n Whether DMA activity ceases after a programmed

number of DMA cycles

n The relative priority of the DMA channel with re-

spect to the other DMA channel

n Whether the source address is incremented, decre-

mented, or maintained constant after each transfer

n Whether the source address addresses memory or

I/O space

n Whether the destination address is incremented,

decremented, or maintained constant after trans-

fers

n Whether the destination address addresses mem-

ory or I/O space

DMA Priority

The DMA channels can be programmed so that one

channel is always given priority over the other, or they

can be programmed to alternate cycles when both

have DMA requests pending. DMA cycles always have

priority over internal CPU cycles except between

locked memory accesses or word accesses to odd

memory locations. However, an external bus hold

takes priority over an internal DMA cycle.

Because an interrupt request cannot suspend a DMA

operation and the CPU cannot access memory during

a DMA cycle, interrupt latency time suffers during se-

quences of continuous DMA cycles. An NMI request,

however, causes all internal DMA activity to halt. This

allows the CPU to respond quickly to the NMI request.

ASYNCHRONOUS SERIAL PORTS

The Am186ED/EDLV microcontrollers provide two in-

dependent asynchronous serial ports. These ports pro-

vide full-duplex, bidirectional data transfer using

several industry-standard communications protocols.

The serial ports can be used as sources or destinations

of DMA transfers.

20-bit Adder/Subtractor

DMA

Control

Logic

Request

Selection

Logic

Adder Control

Logic

Channel Control Register 1

Channel Control Register 0

DRQ1/Serial Port

DRQ0/Serial Port

Timer Request

Interrupt

Request

Transfer Counter Ch. 1

Destination Address Ch. 1

Destination Address Ch. 0

Transfer Counter Ch. 0

Source Address Ch. 1

Source Address Ch. 0

Internal Address/Data Bus

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