AM186ED-20KCSLASHW datasheet(13/88 Pages) AMD

13 / 88 page

Am186ED/EDLV Microcontrollers

PRELI M INARY

F T

Enhanced Refresh Control Unit

The refresh control unit (RCU) is enhanced with two

additional bits in the refresh counter to allow for longer

refresh periods. The address generated during a

refresh has been fixed to FFFFFh. When either bank of

DRAM is enabled and the RCU is enabled, a CAS-

before-RAS refresh will be generated based on the

time period coded into the refresh counter.

Option to Overlap DRAM with PCS

The peripheral chip selects (PCS0–PCS6) can overlap

DRAM blocks with different wait states without external

or internal bus contention. The RAS0 or RAS1 will

assert along with the appropriate PCS. The UCAS and

LCAS will not assert, preventing the DRAM from writing

erroneously or driving the data bus during a read. The

PCS must have the same or higher number of wait

states than the DRAM. The PCS bus width will be

determined by the LSIZ or USIZ bus widths as

programmed in the AUXCON register.

Additional Serial Port Mode for DMA

Support of 9-bit Protocols

A mode 7 was added to the serial port which enhances

the direct memory access (DMA) support for 9-bit

protocols. Using mode 2, the serial port can be

programmed to interrupt only if the 9th bit is set,

ignoring all 9th bit cleared byte receptions. Mode 3

receives all bytes, whether the 9th bit is set or cleared.

Mode 7 also receives all bytes whether the 9th bit is set

or cleared, but now an interrupt is generated when the

9th bit is set. This allows the DMA to service all

receptions, but also allows the CPU to intervene when

the trailer (9th bit set) is received. In all modes using

DMA, the interrupts other than transmitter ready and

character received interrupts can still be generated.

This allows the DMA to handle the standard sending

and receiving characters while the CPU can intervene

when a non-standard event (e.g., framing error)

occurs.

Option to Boot from 8- or 16-bit Memory

The Am186ED/EDLV microcontrollers can boot from 8-

or 16-bit-wide non-volatile memory, based on the state

of the S2/BTSEL pin. If S2/BTSEL is pulled High or left

floating, an internal pullup sets the boot mode option to

16-bit. If S2/BTSEL is pulled resistively Low during

reset, the boot mode option is for 8-bit. The status of

the S2/BTSEL pin is latched on the rising edge of reset.

If the 8-bit boot option is selected, the width of the

memory region associated with UCS can be changed

in the AUXCON register. This allows for cheaper 8-bit-

w i de m emor y t o be used f o r boo tin g th e

microcontroller, while speed-critical code and data can

be executed from 16-bit-wide lower memory. Eight-bit

or 16-bit-wide peripherals can be used in the memory

area between LCS and UCS or in the I/O space. The

entire memory map can be set to 16-bit or 8-bit or

mixed between 8-bit and 16-bit based on the USIZ,

LSIZ, MSIZ, and IOSIZ bits in the AUXCON register.

Improved External Bus Master Support

When the bus is arbitrated away from the Am186ED/

EDLV microcontrollers using the HOLD pin, the chip

selects are driven High (negated) and then held High

with an internal ~10-kohm pullup. This allows external

bus masters to assert the chip selects by externally

pulling them Low, without having to combine the chip

selects from the Am186ED/EDLV microcontrollers and

the external bus master in logic external to the

Am186ED/EDLV microcontrollers. This internal pullup

is activated for any bus arbitration, even if the pin is

being used as a PIO input.

PSRAM Controller Removed

The PSRAM mode found on the Am186ES/ESLV

microcontrollers has been removed and replaced with

a DRAM controller. This includes removal of the variant

PSRAM LCS timing and refresh strobe on MCS3.

AM186ED-20KC/W 数据表(PDF) 13 Page - Advanced Micro Devices

AM186ED-20KC/W 数据表(HTML) 13 Page - Advanced Micro Devices

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