AM186ED-20KCSLASHW datasheet(46/88 Pages) AMD

46 / 88 page

Am186ED/EDLV Microcontrollers

PRELI M INARY

F T

The following diagram shows the behavior of a system

for a typical waveform.

The interrupt service routine (ISR) for the INT2 and

INT4 interrupts should examine the current count of the

associated timer, timer 1 for INT2, and timer 0 for INT4,

in order to determine the pulse width. The ISR should

then reset the timer count register in preparation for the

next pulse.

Since the timers count at one quarter of the processor

clock rate, this determines the maximum resolution that

can be obtained. Further, in applications where the

pulse width may be short, it may be necessary to poll

the INT2 and INT4 request bits in the interrupt request

ing and returning from an interrupt. Overflow condi-

tions, where the pulse width is greater than the

maximum count of the timer, can be detected by moni-

toring the Maximum Count (MC) bit in the associated

timer or by setting the INT bit to enable timer interrupt

requests.

DIRECT MEMORY ACCESS

Direct memory access (DMA) permits transfer of data

between memory and peripherals without CPU involve-

ment. The DMA unit shown in Figure 10, provides two

high-speed DMA channels. Data transfers can occur

between memory and I/O spaces (e.g., memory to I/O)

or within the same space (e.g., memory to memory or

I/O to I/O). Table 9 shows maximum DMA transfer

rates.

The DMA channels can be directly connected to the

asynchronous serial ports. DMA and serial port transfer

is accomplished by programming the DMA controller to

perform transfers between a data source in memory or

I/O space and a serial port transmit or receive register.

The two DMA channels can support one serial port in

full-duplex mode or two serial ports in half-duplex

mode.

Either bytes or words can be transferred to or from

even or odd addresses. However, word DMA transfers

to or from memory configured for 8-bit accesses are

not supported. Only two bus cycles (a minimum of eight

clocks) are necessary for each data transfer.

Each channel accepts a DMA request from one of four

sources: the channel request pin (DRQ1–DRQ0),

Timer 2, a serial port, or the system software. The

channels can be programmed with different priorities in

the event of a simultaneous DMA request or if there is

a need to interrupt transfers on the other channel.

DMA Operation

Each channel has six registers in the peripheral control

block that define specific channel operations. The DMA

registers consist of a 20-bit source address (two regis-

ters), a 20-bit destination address (two registers), a 16-

bit transfer count register, and a 16-bit control register.

The DMA Transfer Count Register (DTC) specifies the

number of DMA transfers to be performed. Up to 64K

of byte or word transfers can be performed with auto-

matic termination. The DMA control registers define the

channel operation. All registers can be modified dur-

ing any DMA activity. Any changes made to the DMA

registers are reflected immediately in DMA operation.

Table 9.

Am186ED/EDLV Microcontrollers

Maximum DMA Transfer Rates

INT2

INT4

INT2

Ints generated

TMR1 enabled

TMR0 enabled

Type of

Synchronization

Selected

Maximum DMA

Transfer Rate (Mbytes)

MHz

Unsynchronized

8.25

6.25

Source Synchronized

8.25

6.25

Destination Synchronized

(CPU needs bus)

6.6

5.5

4.16

3.3

Destination Synch

(CPU does not need bus)

86.6

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