AM186ED-20KCSLASHW datasheet(37/88 Pages) AMD

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Am186ED/EDLV Microcontrollers

PRELI M INARY

F T

Table 6.

DRAM Pin Interface

Programmable Bus Sizing

The Am186ED/EDLV microcontrollers allow program-

mability for data bus widths through fields in the Auxil-

iary Configuration Register (AUXCON) , as shown in

Table 7. The USIZ bit in AUXCON is only configurable

if the boot mode is 8-bit at reset.

The width of the data access should not be modified

while the processor is fetching instructions from the as-

sociated address space.

Table 7.

Programming the Bus Width of

Am186ED/EDLV Microcontrollers

Note:

1. UCS width on reset is determined by the S2/BTSEL

pin. If UCS boots as a 16-bit space, it is not re-con-

figurable to 8-bit.

Byte-Write Enables

The Am186ED/EDLV microcontrollers provide the

WHB (Write High Byte) and WLB (Write Low Byte) sig-

nals, which act as byte-write enables.

WHB is the logical OR of BHE and WR. WHB is Low

when BHE and WR are both Low. WLB is the logical

OR of A0 and WR. WLB is Low when A0 and WR are

both Low.

The byte-write enables are driven in conjunction with

the nonmultiplexed address bus as required for the

write timing requirements of common SRAMs.

Data Strobe Bus Interface Option

The Am186ED/EDLV microcontrollers provide an

asynchronous bus interface that allows the use of 68K-

type peripherals. This implementation combines a DS

data strobe signal (multiplexed with DEN) with an asyn-

chronous ARDY ready input. When DS is asserted, the

data and address signals are valid.

A chip select signal, ARDY, DS, and other control sig-

nals (RD/WR) can control the interface of 68K-type ex-

ternal peripherals to the AD bus.

DRAM INTERFACE

The Am186ED/EDLV microcontrollers support up to

two banks of DRAM. The use of DRAM can signifi-

cantly reduce the memory costs for applications using

more than 64K of RAM. No performance is lost except

for the slight overhead of periodically refreshing the

DRAM. The lower bank of DRAM uses the LCS space.

The upper bank of DRAM uses the UCS space. Either,

neither, or both banks can be activated. When either

bank is activated, the UCAS and LCAS are enabled,

and the DRAM address multiplexing is enabled on the

A19–A0 bus. When DRAM is activated, the corre-

sponding memory bus size should be set to 16-bit. The

use of 8-bit-wide DRAM is not supported. All refreshes

to DRAM are 7 clocks long. The refreshes must be sep-

arately enabled in the RCU.

The improved memory timing specifications of the

Am186ED/EDLV microcontrollers allow for zero-wait-

state operation using 50-ns DRAM at a 40-MHz clock

speed. 60-ns DRAM requires one wait state at 40 MHz

and zero wait states at 33 MHz and below. 70-ns

DRAM requires two wait states at 40 MHz, one wait

state at 33 MHz, and zero wait states at 25 MHz and

below. This reduces overall system cost by enabling

the use of commonly available memory speeds and

taking advantage of DRAM’s lower cost per bit over

SRAM.

AM186ED/EDLV

Microcontroller Pins

DRAM Pin

MA0

MA1

MA2

MA3

MA4

A11

MA5

A13

MA6

A15

MA7

A17

MA8

RAS0RAS (Bank 0)

RAS1RAS (Bank 1)

UCAS

UCAS (AD15–AD8 Byte)

LCAS

LCAS (AD7–AD0 Byte)

Space

AUXCON

Field

Value

Bus

Width

Comments

UCS

USIZ

16 bits

Dependent

on boot

option1

8 bits

LCS

LSIZ

16 bits

Default

8 bits

I/O

IOSIZ

16 bits

Default

8 bits

Other

MSIZ

16 bits

Default

8 bits

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