AM186ED-20KCSLASHW datasheet(44/88 Pages) AMD

44 / 88 page

Am186ED/EDLV Microcontrollers

PRELI M INARY

F T

MCS chip selects, or they can be configured to access

the 64-Kbyte I/O space.

The PCS pins are not active on reset. PCS6–PCS5 can

be programmed for zero to three wait states. PCS3–

PCS0 can be programmed for four additional wait-state

values: 5, 7, 9, and 15.

The AUXCON register can be used to configure PCS

for 8-bit or 16-bit accesses. The bus width of the PCS

range is determined by the width of the non-UCS/non-

LCS memory range or by the width of the I/O area.

Unlike the UCS and LCS chip selects, the PCS outputs

assert with the multiplexed AD address bus. Each

peripheral chip select asserts over a 256-byte address

range, which is twice the address range covered by

peripheral chip selects in the 80C186/188 microcon-

trollers.

The PCS allows for overlap in memory space with the

DRAM (RAS0, RAS1) space. Overlap of the PCS with

LCS, MCS, or UCS in a non-DRAM mode is not recom-

mended. If overlap of the PCS with MCS, LCS, or UCS

occurs, the same number of wait states and external

ready must be used. If overlap of PCS with DRAM

space occurs, the DRAM controller will assert RAS and

stop the CAS signal from asserting. This will not modify

the contents of the DRAM and the access will continue

as a normal PCS access. When overlapping the PCS

with DRAM, the number of wait states can be different

for PCS space. PCS wait states must be greater than

or equal to DRAM wait states. The ready and wait

states will be determined by the PCS programming in

the MPCS and PACS registers.

PCS space should not contain the address FFFFFh,

which is the address used for a refresh cycle. The

AD15–AD0 bus will drive FFFFh during a refresh cycle

for the address portion of cycle.

REFRESH CONTROL UNIT

The refresh control unit (RCU) automatically generates

refresh bus cycles when enabled. After a programma-

ble period of time, the RCU generates a CAS-before-

RAS refresh bus cycle. The RCU should not be en-

abled if at least one bank of DRAM is not enabled. All

refreshes will be 7 clocks, no matter how the DRAM

wait states are programmed. During a refresh cycle,

the A19–A0 bus is undefined; the AD15–AD0 bus is

driven with all 1s (FFFFh). The PCS and MCS chip se-

lects are decoded by the processor using a 20-bit ver-

sion of the AD bus. The highest four bits of this internal

bus are not available externally; however, internally

these bits are set to all 1s during a refresh cycle, result-

ing in the 20-bit address FFFFFh. For this reason, the

MCS and PCS chip selects should not contain the ad-

dress FFFFFh while DRAM is enabled.

INTERRUPT CONTROL UNIT

The Am186ED/EDLV microcontrollers can receive in-

terrupt requests from a variety of sources, both internal

and external. The internal interrupt controller arranges

these requests by priority and presents them one at a

time to the CPU.

There are up to eight external interrupt sources on the

Am186ED/EDLV microcontrollers—seven maskable

interrupt pins and one nonmaskable interrupt (NMI)

pin. In addition, there are eight internal interrupt

sources (three timers, two DMA channels, two asyn-

chronous serial ports, and the Watchdog Timer NMI)

that are not connected to external pins. INT5 and INT6

are multiplexed with DRQ0 and DRQ1. These two in-

terrupts are available if the associated DMA is not en-

abled or is being used with internal synchronization.

The Am186ED/EDLV microcontrollers provide up to six

interrupt sources not present on the 80C186 and

80C188 microcontrollers. There are up to three addi-

tional external interrupt pins—INT4, INT5, and INT6.

These pins operate much like the INT3–INT0 interrupt

pins on the 80C186 and 80C188 microcontrollers.

There are also two internal interrupts from the serial

ports and the watchdog timer can generate interrupts.

INT5 and INT6 are multiplexed with the DMA request

signals, DRQ0 and DRQ1. If a DMA channel is not en-

abled, or if it is not using external synchronization, then

the associated pin can be used as an external interrupt.

INT5 and INT6 can also be used in conjunction with the

DMA terminal count interrupts.

The seven maskable interrupt request pins can be

used as direct interrupt requests. INT4–INT0 can be ei-

ther edge-triggered or level-triggered. INT6 and INT5

are edge-triggered only. In addition, INT0 and INT1 can

be configured in cascade mode for use with an external

82C59A-compatible interrupt controller. When INT0 is

configured in cascade mode, the INT2 pin is automati-

cally configured in its INTA0 function. When INT1 is

configured in cascade mode, the INT3 pin is automati-

cally configured in its INTA1 function. An external inter-

rupt controller can be used as the system master by

programming the internal interrupt controller to operate

in slave mode. INT6–INT4 are not available in slave

mode.

Interrupts are automatically disabled when an interrupt

is taken. Interrupt-service routines (ISRs) may

re-enable interrupts by setting the IF flag. This allows

interrupts of greater or equal priority to interrupt the

currently executing ISR. Interrupts from the same

source are disabled as long as the corresponding bit in

the interrupt in-service register is set. INT1 and INT0

provide a special bit to enable special fully nested

mode. When configured in special fully nested mode,

the interrupt source may generate a new interrupt

regardless of the setting of the in-service bit.

AM186ED-20KC/W 数据表(PDF) 44 Page - Advanced Micro Devices

AM186ED-20KC/W 数据表(HTML) 44 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

数据表下载