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AM186ED-20KC/W 数据表(PDF) 70 Page - Advanced Micro Devices |
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AM186ED-20KC/W 数据表(HTML) 70 Page - Advanced Micro Devices |
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70 / 88 page ![]() 70 Am186ED/EDLV Microcontrollers PRELI M INARY D RA F T SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges DRAM As guaranteed by design, the following table shows the minimum time for RAS assertion to RAS assertion. These minimums correlate to DRAM spec tRC. Parameter Preliminary Unit 20 MHz 25 MHz 33 MHz 40 MHz No. Symbol Description Min Max Min Max Min Max Min Max General Timing Responses 101 tCHCAV CLKOUTA Low to Column Address Valid 0250 20015012 ns 102 tCLRA CLKOUTA Low to RAS Active 3253 20315312 ns 103 tCHRX CLKOUTA High to RAS Inactive 3253 20315312 ns 104 tCHCA CLKOUTA High to CAS Active 3253 20315312 ns 105 tCLCX CLKOUTA Low to CAS Inactive 3253 20315312 ns 106 tCHRA CLKOUTA High to RAS Active 3253 20315312 ns 107 tCLRX CLKOUTA Low to RAS Inactive 3253 20315312 ns 108 tRP0W RAS Inactive Pulse Width with 0 Wait States 60 — 50 — 40 — 30 — ns 109 tRP1W RAS Inactive Pulse Width with 1 or More Wait States 70 — 60 — 50 — 40 — ns 110 tRD0W RAS To Column Address Delay Time with 0 Wait States 25 — 20 — 15 — 15 — ns 111 tRD1W RAS to Column Address Delay Time with 1 or More Wait States 30 — 25 — 20 — 15 — ns Wait States 012 3 40 MHz 90 110 130 150 33 MHz 110 130 150 170 25 MHz 130 150 170 190 20 MHz 150 170 190 210 |
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