AM186ED-20KCSLASHW datasheet(40/88 Pages) AMD

40 / 88 page

Am186ED/EDLV Microcontrollers

PRELI M INARY

F T

CLOCK AND POWER MANAGEMENT

The clock an d po wer m an age me nt u nit of the

Am186ED/EDLV microcontrollers includes a phase-

locked loop (PLL) and a second programmable system

clock output (CLKOUTB).

Phase-Locked Loop

In a traditional 80C186/188 microcontroller design, the

crystal frequency is twice that of the desired internal

clock. Because of the PLL on the Am186ED/EDLV mi-

crocontrollers, the internal clock generated by the

Am186ED/EDLV microcontrollers (CLKOUTA) is the

same frequency as the crystal. The PLL takes the crys-

tal inputs (X1 and X2) and generates a 45–55% (worst

case) duty cycle intermediate system clock of the same

frequency. This removes the need for an external 2x

oscillator, reducing system cost. The PLL is reset dur-

ing power-on reset by an on-chip power-on reset

(POR) circuit.

Crystal-Driven Clock Source

The internal oscillator circuit of the Am186ED/EDLV

microcontrollers is designed to function with a parallel

resonant fundamental or third overtone crystal. Be-

cause of the PLL, the crystal frequency should be

equal to the processor frequency. Do not replace a

crystal with an LC or RC equivalent.

The X1 and X2 signals are connected to an internal in-

verting amplifier (oscillator) that provides, along with

the external feedback loading, the necessary phase

shift (Figure 8). In such a positive feedback circuit, the

inverting amplifier has an output signal (X2) 180 de-

grees out of phase of the input signal (X1).

The external feedback network provides an additional

180-degree phase shift. In an ideal system, the input to

X1 will have 360 or zero degrees of phase shift. The ex-

ternal feedback network is designed to be as close to

ideal as possible. If the feedback network is not provid-

ing necessary phase shift, negative feedback dampens

the output of the amplifier and negatively affects the op-

eration of the clock generator. Values for the loading on

X1 and X2 must be chosen to provide the necessary

phase shift and crystal operation.

Selecting a Crystal

When selecting a crystal, the load capacitance should

always be specified (CL). This value can cause vari-

ance in the oscillation frequency from the desired spec-

ified value (resonance). The load capacitance and the

loading of the feedback network have the following re-

lationship:

where CS is the stray capacitance of the circuit. Placing

the crystal and CL in series across the inverting ampli-

fier and tuning these values (C1, C2) allows the crystal

to oscillate at resonance. This relationship is true for

both fundamental and third-overtone operation. Finally,

there is a relationship between C1 and C2. To enhance

the oscillation of the inverting amplifier, these values

need to be offset with the larger load on the output (X2).

Equal values of these loads tend to balance the poles

of the inverting amplifier.

The characteristics of the inverting amplifier set limits

on the following parameters for crystals:

ESR (Equivalent Series Resistance) ...... 60

Ω max

Drive Level .............................................. 1 mW max

The recommended range of values for C1 and C2 are

as follows:

C1 ..................................................................15 pF ± 20%

C2 ..................................................................22 pF ± 20%

The specific values for C1 and C2 must be determined

by the designer and are dependent on the characteris-

tics of the chosen crystal and board design.

Figure 8.

Am186ED/EDLV Microcontrollers Oscillator Configurations

(C1 ⋅ C2)

(C1 + C2)

CL =

+ CS

Crystal

Am186ED/EDLV

200 pF

Note 1

Note 1: Use for Third Overtone Mode

XTAL Frequency

L1 Value (Max)

20 MHz

µH ±20%

25 MHz

8.2

µH ±20%

33 MHz

4.7

µH ±20%

40 MHz

3.0

µH ±20%

b. Crystal Configuration

a. Inverting Amplifier Configuration

Crystal

Microcontrollers

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