AM186ED-20KCSLASHW datasheet(30/88 Pages) AMD

30 / 88 page

Am186ED/EDLV Microcontrollers

PRELI M INARY

F T

RTS0/RTR0/PIO20

Ready-to-Send 0 (output, asynchronous)

Ready-to-Receive 0 (output, asynchronous)

RTS0—This pin provides the Ready-to-Send signal for

asynchronous serial port 0 when the RTS0 bit in the

AUXCON register is 1 and hardware flow control is

enabled for the port (FC bit in the serial port 0 control

associated serial port transmit register contains data

that has not been transmitted.

RTR0—This pin provides the Ready-to-Receive signal

for asynchronous serial port 0 when the RTS0 bit in the

AUXCON register is 0 and hardware flow control is

enabled for the port (FC bit in the serial port 0 control

associated serial port receive register does not contain

valid, unread data.

RXD0/PIO23

Receive Data 0 (input, asynchronous)

This pin supplies asynchronous serial receive data

from the system to asynchronous serial port 0.

RXD1/PIO28

Receive Data 1 (input, asynchronous)

This pin supplies asynchronous serial receive data

from the system to asynchronous serial port 1.

S2/BTSEL

Bus Cycle Status (output, three-state,

synchronous)

Boot Mode Select

S2—This pin indicates to the system the type of bus

cycle in progress. S2 can be used as a logical memory or

I/O indicator. S2–S0 float during bus hold and hold

acknowledge conditions. The S2–S0 pins are encoded as

shown in Table 4.

BTSEL—The Am186ED/EDLV microcontrollers can

boot from 8- or 16-bit wide nonvolatile memory, based

on the state of the BTSEL pin. If BTSEL is pulled High

or left floating, an internal pullup sets the boot mode

option to 16-bit. If BTSEL is pulled resistively Low

during reset, the 8-bit boot mode option is selected.

The status of the BTSEL pin is latched on the rising

edge of reset. If 8-bit mode is selected, the width of the

memory region associated with UCS can be changed

in the AUXCON register.

This signal should never be tied to VCC or VSS directly

since this pin is driven during normal operation. This

signal should be tied Low with an external resistor if the

8-bit boot mode is to be used. The internal pullup

resistor on BTSEL is ~9 kohm.

S1–S0

Bus Cycle Status (output, three-state,

synchronous)

These pins indicate to the system the type of bus cycle

in progress. S1 can be used as a data transmit or

receive indicator. S1–S0 float during bus hold and hold

acknowledge conditions. The S2–S0 pins are encoded

as shown in Table 4.

Table 4.

Bus Cycle Encoding

S6/CLKDIV2/PIO29

Bus Cycle Status Bit 6 (output, synchronous)

Clock Divide by 2 (input, internal pullup)

S6—During the second and remaining periods of a

cycle (t2, t3, and t4), this pin is asserted High to indicate

a DMA-initiated bus cycle. During a bus hold or reset

condition, S6 floats.

CLKDIV2—If S6/CLKDIV2/PIO29 is held Low during

power-on reset, the chip enters clock divided by 2

mode where the processor clock is derived by dividing

the external clock input by 2. If this mode is selected,

the PLL is disabled. The pin is sampled on the rising

edge of RES.

If S6 is to be used as PIO29 in input mode, the device

driving PIO29 must not drive the pin Low during power-

on reset. S6/CLKDIV2/PIO29 defaults to a PIO input

with pullup, so the pin does not need to be driven High

externally.

SRDY/PIO6

Synchronous Ready (input, synchronous,

level-sensitive)

This pin indicates to the microcontroller that the

addressed memory space or I/O device will complete a

data transfer. The SRDY pin accepts an active High

input synchronized to CLKOUTA.

Using SRDY instead of ARDY allows a relaxed system

timing because of the elimination of the one-half clock

period required to internally synchronize ARDY. To

a l ways asse r t the r eady con d it ion t o the

S2/BTSEL

S1S0

Bus Cycle

Interrupt acknowledge

Read data from I/O

Write data to I/O

Halt

Instruction fetch

Read data from memory

Write data to memory

None (passive)

AM186ED-20KC/W 数据表(PDF) 30 Page - Advanced Micro Devices

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