AM186ED-20KCSLASHW datasheet(33/88 Pages) AMD

33 / 88 page

Am186ED/EDLV Microcontrollers

PRELI M INARY

F T

FUNCTIONAL DESCRIPTION

The Am186ED/EDLV microcontrollers are based on

the architecture of the 80C186 and 80C188 microcon-

trollers. The Am186ED/EDLV microcontrollers function

in the enhanced mode of earlier generations of 80C186

and 80C188 microcontrollers. Enhanced mode in-

cludes system features such as power-save control.

Each of the 8086, 8088, 80186, and 80188 microcon-

trollers contains the same basic set of registers, in-

structions, and addressing modes. The Am186ED/

EDLV microcontrollers are backward-compatible with

the 80C186 and 80C188 microcontrollers.

A full description of all the Am186ED/EDLV microcon-

troller registers and instructions is included in the

Am186ED/EDLV Microcontrollers User’s Manual, or-

der# 21335A.

Memory Organization

Memory is organized in sets of segments. Each seg-

ment is a linear contiguous sequence of 64K (216) 8-bit

bytes. Memory is addressed using a two-component

address that consists of a 16-bit segment value and a

16-bit offset. The 16-bit segment values are contained

in one of four internal segment registers (CS, DS, SS,

or ES). The physical address is calculated by shifting

the segment value left by 4 bits and adding the 16-bit

offset value to yield a 20-bit physical address (see Fig-

ure 3). This allows for a 1-Mbyte physical address size.

All instructions that address operands in memory must

specify the segment value and the 16-bit offset value.

For speed and compact instruction encoding, the seg-

ment register used for physical address generation is

implied by the addressing mode used (see Table 5).

Figure 3.

Two-Component Address

I/O Space

The I/O space consists of 64K 8-bit or 32K 16-bit ports.

Separate instructions (IN, INS and OUT, OUTS) ad-

dress the I/O space with either an 8-bit port address

specified in the instruction, or a 16-bit port address in

the DX register. Eight-bit port addresses are zero-ex-

tended such that A15–A8 are Low. I/O port addresses

00F8h through 00FFh are reserved.

Table 5.

Segment Register Selection Rules

Segment

Base

Logical

Address

Shift

Left

4 Bits

Physical Address

To Memory

Offset

Memory Reference

Needed

Segment Register Used

Implicit Segment Selection Rule

Instructions

Code (CS)

Instructions (including immediate data)

Local Data

Data (DS)

All data references

Stack

Stack (SS)

All stack pushes and pops;

any memory references that use BP Register

External Data (Global)

Extra (ES)

All string instruction references that use the DI Register as an index

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