AM186ED-20KCSLASHW datasheet(25/88 Pages) AMD

25 / 88 page

Am186ED/EDLV Microcontrollers

PRELI M INARY

F T

INT4/PIO30

Maskable Interrupt Request 4 (input,

asynchronous)

This pin indicates to the microcontroller that an

interrupt request has occurred. If the INT4 pin is not

masked, the microcontroller then transfers program

execution to the location specified by the INT4 vector in

the microcontroller interrupt vector table.

Interrupt requests are synchronized internally, and can

be edge-triggered or level-triggered. To guarantee

interrupt recognition, the requesting device must

co ntin ue as se r t i ng INT4 u n ti l the r e q ues t is

acknowledged.

When pulse width demodulation mode is enabled, the

INT4 signal is used internally to indicate a High-to-Low

transition on the PWD signal. When pulse width

demodulation mode is enabled, INT4/PIO30 can be

used as a PIO.

LCS/ONCE0/RAS0

Lower Memory Chip Select (output, synchronous,

internal pullup)

ONCE Mode Request 0 (input)

Row Address Strobe 0

LCS—This pin indicates to the system that a memory

access is in progress to the lower memory block. The

base address and size of the lower memory block are

programmable up to 512 Kbytes. LCS is configured for

8-bit or 16-bit bus size by the auxiliary configuration

LCS is three-stated and held resistively High during a

bus hold condition. In addition, LCS has an ~9-kohm

internal pullup resistor that is active during reset.

ONCE0—During reset, this pin and ONCE1 indicate to

the microcontroller the mode in which it should operate.

ONCE0 and ONCE1 are sampled on the rising edge of

RES. If both pins are asserted Low, the microcontroller

enters ONCE mode; otherwise, it operates normally.

In ONCE mode, all pins assume a high-impedance

state and remain in that state until a subsequent reset

occurs. To guarantee that the microcontroller does not

inadvertently enter ONCE mode, ONCE0 has a weak

internal pullup resistor that is active only during reset.

RAS0—This pin is the row address strobe for the lower

D R AM block . The s e l e ction of RAS 0 or LCS

functionality, along with their configurations, are set

using the LMCS register.

RAS0 is three-stated and held resistively High during a

bus hold condition. In addition, RAS0 has a weak

internal pullup resistor that is active during reset.

MCS0/PIO14

Midrange Memory Chip Select 0 (output,

synchronous, internal pullup)

This pin indicates to the system that a memory access

is in progress to the corresponding region of the

midrange memory block. The base address and size of

the midrange memory block are programmable. MCS0

can be programmed as the chip select for the entire

middle chip select address range. This mode is

recommended when using DRAM since the MCS1,

MCS2, and MCS3 chip selects function as RAS and

CAS signals for the DRAM interface and are not

available as chip selects.

MCS0 is configured for 8-bit or 16-bit bus size by the

auxiliary configuration register. MCS0 is three-stated

and held resistively High during a bus hold condition. In

addition, MCS0 has a weak internal pullup resistor that

is active during reset.

MCS1/UCAS/PIO15

Midrange Memory Chip Select (output,

synchronous, internal pullup)

Upper Column Address Strobe

This pin indicates to the system that a memory access

is in progress to the corresponding region of the

midrange memory block. The base address and size of

the midrange memory block are programmable. MCS1

is configured for 8-bit or 16-bit bus size via the auxiliary

configuration register.

MCS1 is three-stated and held resistively High during a

bus hold condition. In addition, MCS1 has a weak

internal pullup resistor that is active during reset.

If MCS0 is programmed to be active for the entire

middle chip-select range, then this signal is available

as a PIO or a DRAM control. If this signal is not

programmed as a PIO or DRAM control and if MCS0 is

programmed for the entire middle chip-select range,

this signal operates normally.

UCAS—When either bank of DRAM is activated, the

UCAS functionality is enabled. The UCAS activates

when the DRAM access is for the AD15–AD8 byte.

UCAS also activates at the start of a DRAM refresh

access.

UCAS is three-stated and held resistively High during a

bus hold condition. In addition, UCAS has a weak

internal pullup resistor that is active during reset.

MCS2/LCAS/PIO24

Midrange Memory Chip Select (output,

synchronous, internal pullup)

Lower Column Address Strobe

This pin indicates to the system that a memory access

is in progress to the corresponding region of the

midrange memory block. The base address and size of

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