AM186ED-20KCSLASHW datasheet(48/88 Pages) AMD

48 / 88 page

Am186ED/EDLV Microcontrollers

PRELI M INARY

F T

The asynchronous serial ports support the following

features:

n Full-duplex operation

n Direct memory access (DMA) from the serial ports

n 7-bit, 8-bit, or 9-bit data transfers

n Odd, even, or no parity

n One stop bit

n Long or short break character recognition

n Error detection

— Parity errors

— Framing errors

— Overrun errors

— Break character recognition

n Hardware handshaking with the following select-

able control signals:

— Clear-to-send (CTS)

— Enable-receiver-request (ENRX)

— Ready-to-send (RTS)

— Ready-to-receive (RTR)

n DMA to and from the serial ports

n Separate maskable interrupts for each port

n Multidrop protocol (9-bit) support

n Independent baud rate generators

n Maximum baud rate of 1/16th of the CPU clock

n Double-buffered transmit and receive

n Programmable interrupt generation for transmit, re-

ceive, and/or error detection

DMA Transfers through the Serial Port

The DMA channels can be directly connected to the

asynchronous serial ports. DMA and serial port transfer

is accomplished by programming the DMA controller to

perform transfers between a memory or I/O space and

a serial port transmit or receive register. The two DMA

channels can support one serial port in full-duplex

mode or two serial ports in half-duplex mode. See the

DMA Control register descriptions in the

Am186ED/

EDLV Microcontrollers User’s Manual, order# 21335A

for more information.

PROGRAMMABLE I/O (PIO) PINS

There are 32 pins on the Am186ED/EDLV microcon-

trollers that are available as user-programmable I/O

signals. Table 2 on page 29 and Table 3 on page 29 list

the PIO pins. Each of these pins can be used as a user-

programmable input or output signal if the normal

shared function is not needed.

If a pin is enabled to function as a PIO signal, the pre-

assigned signal function is disabled and does not affect

the level on the pin. A PIO signal can be configured to

operate as an input or output with or without a weak

pullup or pulldown, or as an open-drain output.

After power-on reset, the PIO pins default to various

configurations. The column titled

Power-On Reset Sta-

tus in Table 2 on page 29 and Table 3 on page 29 lists

the defaults for the PIOs. The system initialization code

must reconfigure the PIOs as required.

The A19–A17 address pins default to normal operation

on power-on reset, allowing the processor to correctly

begin fetching instructions at the boot address

FFFF0h. The DT/R, DEN, and SRDY pins also default

to normal operation on power-on reset.

Note that emulators use A19, A18, A17, S6, and UZI.

In environments where an emulator is needed, these

pins must be configured for normal function—not as

PIOs.

If the AD15–AD0 bus override is enabled on power-on

reset, then S6/CLKDIV2 and UZI revert to normal oper-

ation instead of PIO input with pullup. If BHE/ADEN is

held Low during power-on reset, the AD15–AD0 bus

override is enabled.

When the PCS or MCS are used as PIO inputs (only)

and the bus is arbitrated, an internal pullup of ~10

kohms is activated, even if the pullup option for the PIO

is not selected.

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