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XIO2000 数据表(PDF) 134 Page - Texas Instruments |
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XIO2000 数据表(HTML) 134 Page - Texas Instruments |
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134 / 150 page  Memory-Mapped TI Proprietary Register Space 122 November 2005 SCPS097B Table 6−13. Serial IRQ Edge Control Register Description (Continued) BIT FIELD NAME ACCESS DESCRIPTION 3† IRQ3_MODE RW IRQ 3 edge mode 0 = Edge mode (default) 1 = Level mode 2† IRQ2_MODE RW IRQ 2 edge mode 0 = Edge mode (default) 1 = Level mode 1† IRQ1_MODE RW IRQ 1 edge mode 0 = Edge mode (default) 1 = Level mode 0† IRQ0_MODE RW IRQ 0 edge mode 0 = Edge mode (default) 1 = Level mode † These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset. 6.25 Serial IRQ Status Register This register indicates when a level mode IRQ is signaled on the serial IRQ stream. After a level mode IRQ is signaled, a write-back of 1b to the asserted IRQ status bit re-arms the interrupt. IRQ interrupts that are defined as edge mode in the serial IRQ edge control register are not reported in this status register. This register is an alias for the serial IRQ status register in the classic PCI configuration space (offset E4h, see Section 4.74). See Table 6−14 for a complete description of the register contents. Device control memory window register offset: 4Ch Register type: Read/Clear Default value: 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 6−14. Serial IRQ Status Register Description BIT FIELD NAME ACCESS DESCRIPTION 15 IRQ15 RCU IRQ 15 asserted. This bit indicates that the IRQ has been asserted. 0 = Deasserted 1 = Asserted 14 IRQ14 RCU IRQ 14 asserted. This bit indicates that the IRQ has been asserted. 0 = Deasserted 1 = Asserted 13 IRQ13 RCU IRQ 13 asserted. This bit indicates that the IRQ has been asserted. 0 = Deasserted 1 = Asserted 12 IRQ12 RCU IRQ 12 asserted. This bit indicates that the IRQ has been asserted. 0 = Deasserted 1 = Asserted 11 IRQ11 RCU IRQ 11 asserted. This bit indicates that the IRQ has been asserted. 0 = Deasserted 1 = Asserted 10 IRQ10 RCU IRQ 10 asserted. This bit indicates that the IRQ has been asserted. 0 = Deasserted 1 = Asserted 9 IRQ9 RCU IRQ 9 asserted. This bit indicates that the IRQ has been asserted. 0 = Deasserted 1 = Asserted |
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