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XIO2000 数据表(PDF) 143 Page - Texas Instruments |
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XIO2000 数据表(HTML) 143 Page - Texas Instruments |
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143 / 150 page  Electrical Characteristics 131 November 2005 SCPS097B 7.8 PCI Clock Timing Requirements Over Recommended Operating Conditions PARAMETER 33 MHZ 66 MHZ UNITS PARAMETER MIN MAX MIN MAX UNITS tc Cycle time, CLK 30 1 15 30 ns twH Pulse duration (width), CLK high 11 6 ns twL Pulse duration (width), CLK low 11 6 ns trise tfall Slew rate, CLK 1.5 4 1.5 4 V/ns tdc CLKOUT6:0 duty cycle 40% 60% 40% 60% tskew CLKOUT6:0 skew between clock outputs 0.5 0.5 ns tsu Setup time, CLKOUT6:0 stable before PRST is deasserted 100 100 µs 7.9 PCI Bus Timing Requirements Over Recommended Operating Conditions PARAMETER TEST 33 MHZ 66 MHZ UNITS PARAMETER TEST CONDITION MIN MAX MIN MAX UNITS tpd CLK to shared signal valid propagation delay time CL = 50 pF 11 ns tpd CLK to shared signal valid propagation delay time CL = 30 pF 6 ns tpd CLK to shared signal invalid propagation delay time CL = 50 pF 2 ns tpd CLK to shared signal invalid propagation delay time CL = 30 pF 1 ns ton Enable time, high-impedance-to-active delay time from CLK CL = 50 pF 2 ns ton Enable time, high-impedance-to-active delay time from CLK CL = 30 pF 1 ns toff Disable time, active-to-high-impedance delay time from CLK CL = 50 pF 28 ns toff Disable time, active-to-high-impedance delay time from CLK CL = 30 pF 14 ns tsu Setup time on shared signals before CLK valid (rising edge) 7 3 ns th Hold time on shared signals after CLK valid (rising edge) 0 0 ns Note: The PCI shared signals are AD31:0, C/BE3:0, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, LOCK, SERIRQ, PAR, PERR, SERR, and CLKRUN. |
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